[SI-LIST] Re: termination for routing 8 SDRAMs to single Processor
- From: Aravnda G <aavinda12@xxxxxxxxx>
- To: for_si_list@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Fri, 12 Aug 2005 16:49:05 -0700 (PDT)
Hi All,
I have been simulating various topologies for the data lines and found the
following to be working well (within dc, ac spec, good noise margin levels,
etc.):
a balanced T with 45Ohm series termination at the beginning of the T junction.
Does this seem correct or are there any possible issues with this topology?
I tried shunt termination at the controller side but this really reduced the
noise margin to below 50mV though it is otherwise meeting the spec.
Regards,
Alex.
> Hi All,
> I am working with a micro-processor conneted to 8 SDRAM with 12
address lines to all SDRAMs and 32 data lines each to two sets of
four SDRAMs. I was wondering if anyone has managed to route this sort
of topology without using terminations. If so please send information
on topology used. The IO are lvttl compatible at 3.3V. Any input on
routing possibilities is welcome.
>
> Thanks & Regards,
> Alex.
>
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