[SI-LIST] Re: termination for routing 8 SDRAMs to single Processor
- From: "Dimiter Popoff" <dp@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 16 Aug 2005 16:37:50 +0300
Scott,
thanks for the insight. I am less experienced than you are on DDR application,
and for my last design I opted for overdesign (all terminators) simply because
this was safe enough and the cost negligible (no huge quantities expected
so no point spending too much time on simulation etc.).
The design we are talking about, though, is 5 years old. The controller is
a 290 nm device. The clock frequency is 100 MHz. Even if we get all that
100% overshoot would you still claim it can carry enough energy to cause
any problems? (long term as the phenomenon is, it did not show up for
4 years of practically continuous operation). Obviously all
the inputs are clamped to the power rail.
So what would your consulting advise be in that particular case, at these trace
lengths?
If it were "we have to look into it and simulate etc..." (which I doubt it
would be), well, I'd
go elsewhere.
Dimiter
------------------------------------------------------
Dimiter Popoff Transgalactic Instruments
http://www.tgi-sci.com
------------------------------------------------------
-------Original Message-------
> From: Scott McMorrow <scott@xxxxxxxxxxxxx>
> Subject: [SI-LIST] Re: termination for routing 8 SDRAMs to single
> Processor
> Sent: Aug 16 '05 16:06
>
> Dimiter
> You are way off base here. Having worked at a major semiconductor
> corporation in the past, and having consulted on many hundreds of DDR
> designs, I can tell you that there can be controller overshoot risks,
> even with 1" of trace. You do know, of course, that in addition to that
> 1" of trace on your board, there is approximately 1/4" to 1/2" of trace
> (or lead frame ) in the memory package, and 1/2" to 1" of trace in the
> controller package. If we assume 2" of total net length between
> devices, and conservatively say that the propagation delay of the media
> is 150 ps/in, then the one way delay is 300 ps, and the round trip delay
> is 600 ps. This means that any memory signal launched by the RAM with
> an edge rate less than 600 ps will see full overshoot at the receiver in
> the controller. DDR memory devices have some of the fastest driver edge
> rates in the industry. We have measured sub-150 ps edges, and
> simulations show sub-100 ps. We also find that many DDR memory devices
> have extremely low driver output impedance, which exacerbates the issues
> of overshoot, by increasing worst case amplitude.
>
> Now, concerning overshoot stress induced failure, some manufacturers do
> specify dynamic overshoot, and ask that designers limit the overshoot to
> some absolute voltage, and percentage of cycle, or time, above the DC
> voltage limits. It may be that your particular device has this sort of
> tolerance, whether or not specified. On the other hand, it may just be
> that you have not seen a failure, since electromigration is generally a
> long-term statistical issue, and not an absolute failure mode.
>
> Personally, I don't care whether you follow our advise. You are the
> designer on your projects, and you know best. However, if I am in a
> position to advise others, my advise is to limit worst case
> over/undershoot to the within manufacturer's limits. The advise is
> free. You can choose to accept it or not.
>
>
> Best regards,
>
> Scott
>
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> (401) 284-1827 Business
> (401) 284-1840 Fax
>
> http://www.teraspeed.com
>
> Teraspeed® is the registered service mark of
> Teraspeed Consulting Group LLC
>
>
>
> Dimiter Popoff wrote:
>
> >After this thread has been recurring for a week, I'll timeout my promise to
> >no longer post on it, as Steve keeps on posting nonsense on it.
> >
> >So let me see:
> >- the chip spec explicitly says that unlike the 5V tolerant PCI pins the
> memory controller
> > pins are 3.3V only;
> >- I explained there were visible diferences in the behaviour of the two pin
> groups;
> >- and I stated, that the trace length is within an inch or so.
> >
> >And here comes Steve Weir and weighs in with the assumption, that all of the
> >above may be wrong and that an inch long trace can produce enough overshoot
> >at 100 MHz to kill parts if I had not been lucky.
> >Well, I realize selling consulting services may be a priority if that's all
> one has to sell,
> >but after this output as far as it would be up to me the consultant would
> have even
> >more time for posting to the net.
> >
> >------------------------------------------------------
> >Dimiter Popoff Transgalactic Instruments
> >
> >http://www.tgi-sci.com
> >------------------------------------------------------
> >
> >
> >
> >
> >-------Original Message-------
> >
> >
> >>From: steve weir <weirsi@xxxxxxxxxx>
> >>Subject: [SI-LIST] Re: termination for routing 8 SDRAMs to single
> Processor
> >>Sent: Aug 16 '05 13:02
> >>
> >> Navaneeth, thanks, but the RAMs weren't at issue. The controller
> >> was. Dimiter has used that particular controller without termination
> and
> >> experienced reliable operation for 4 years . We discussed reasons why
> that
> >> might be when excessive overshoot can cause damage and premature
> >> failures. Either there wasn't too much overshoot, less likely, or the
> >> component tested was tolerant to the amplitude and duration by design or
> >> good fortune.
> >> Steve.
> >>
> >> At 10:33 AM 8/16/2005 +0530, navaneeth.kumar@xxxxxxxxx wrote:
> >> >Hi,
> >> > Manufacturers like micron and samsung specify in their
> >> > SDRAM(3.3v) datasheet that their inputs can withstand an overshoot
> >> > voltage of 5.6vmax provided the overshoot width is lesser then 3nsec.
> >> >
> >> >regards
> >> >Navaneeth
> >> >
> >> >
> >> >----------
> >> >From: si-list-bounce@xxxxxxxxxxxxx on behalf of Dimiter Popoff
> >> >Sent: Thu 8/11/2005 12:27 PM
> >> >To: steve weir;
> >> >Subject: [SI-LIST] Re: termination for routing 8 SDRAMs to single
> Processor
> >> >
> >> >Memory outputs are separately powered. At least with revision A (which
> >> >was practically unusable) memory outputs would not obey JTAG if
> >> >the memory clock did not work or something like that (PCI did).
> >> >
> >> >It is possible, of course, that the memory inputs have been overdesigned
> >> >to be the same as the PCI ones, but quite unlikely, 5V tolerance is
> >> >not that cheap to make. I guess no one except for the actual chip
> >> >designer can answer that question, so we better cut it here.
> >> >
> >> >Dimiter
> >> >
> >> >------------------------------------------------------
> >> >Dimiter Popoff Transgalactic Instruments
> >> >
> >> ><http://www.tgi-sci.com>http://www.tgi-sci.com
> >> >------------------------------------------------------
> >> >
> >> >
> >> >
> >> >
> >> >-------Original Message-------
> >> > > From: steve weir <weirsi@xxxxxxxxxx>
> >> > > Subject: Re: [SI-LIST] Re: termination for routing 8 SDRAMs to
> >> > single Processor
> >> > > Sent: Aug 11 '05 09:37
> >> > >
> >> > > Dimiter, I know the memory power rail is spec'd for 3.3V, but that
> really
> >> > > doesn't tell us about the drivers / receivers.
> >> > >
> >> > > Steve.
> >> > > At 09:30 AM 8/11/2005 +0300, Dimiter Popoff wrote:
> >> > > >Only the PCI pins are specified to up to 5.5 V input voltage.
> >> > > >The rest are specified at max. 3.3V. (Memory might be 2.5 V max.,
> >> > > >separate power, which in my case is 3.3V - cut and "jumper solder"
> >> > > >selectable to 2.5, but this feature has never been used)..
> >> > > >
> >> > > >Dimiter
> >> > > >
> >> > > >------------------------------------------------------
> >> > > >Dimiter Popoff Transgalactic Instruments
> >> > > >
> >> > > ><http://www.tgi-sci.com>http://www.tgi-sci.com
> >> > > >------------------------------------------------------
> >> > > >
> >> > > >
> >> > > >-------Original Message-------
> >> > > > > From: steve weir <weirsi@xxxxxxxxxx>
> >> > > > > Subject: Re: [SI-LIST] Re: termination for routing 8 SDRAMs to
> >> > > > single Processor
> >> > > > > Sent: Aug 11 '05 09:19
> >> > > > >
> >> > > > > Dimiter, that part has 5V tolerant PCI I/O. If the memory
> I/O's are
> >> > > > > similarly tolerant, it is easy to understand why you don't have
> >> > > > reliability
> >> > > > > issues.
> >> > > > >
> >> > > > > Steve.
> >> > > > >
> >> > > > >
> >> > > > > At 09:07 AM 8/11/2005 +0300, Dimiter Popoff wrote:
> >> > > > > >Like I mentioned, he controller was an 8240 (MPC8240 of
> >> > Motorola, now
> >> > > > > >Freescale).
> >> > > > > >If keeping connections within about an inch or just somewhat
> >> > more length
> >> > > > > >is luck, then I guess I have been lucky.
> >> > > > > >
> >> > > > > >Dimiter
> >> > > > > >
> >> > > > > >------------------------------------------------------
> >> > > > > >Dimiter Popoff Transgalactic Instruments
> >>
> >>
> >>> > > >
> >>> > > ><http://www.tgi-sci.com>http://www.tgi-sci.com
> >>>
> >>>
> >> > > > > > >------------------------------------------------------
> >> > > > > > >
> >> > > > > > >
> >> > > > > > >
> >> > > > > > >
> >> > > > > > >-------Original Message-------
> >> > > > > > > > From: steve weir <weirsi@xxxxxxxxxx>
> >> > > > > > > > Subject: Re: [SI-LIST] Re: termination for routing 8
> SDRAMs to
> >> > > > > > > single Processor
> >> > > > > > > > Sent: Aug 11 '05 09:03
> >> > > > > > > >
> >> > > > > > > > Dimiter, you may have lucked out on that
> one. Repeated, excess
> >> > > > > overshoot
> >> > > > > > > > is well demonstrated to shorten the life of components,
> >> > > > > especially newer
> >> > > > > > > > low voltage devices. What was the controller?
> >> > > > > > > >
> >> > > > > > > > Steve.
> >> > > > > > > > At 08:55 AM 8/11/2005 +0300, Dimiter Popoff wrote:
> >> > > > > > > > >Is about 4 years practically continuous operation good
> enough?
> >> > > > > > > > >The design has demonstrated it.
> >> > > > > > > > >
> >> > > > > > > > >Dimiter
> >> > > > > > > > >
> >> > > > > > > > >------------------------------------------------------
> >> > > > > > > > >Dimiter Popoff Transgalactic Instruments
> >> > > > > > > > >
> >> > > > > > > > ><http://www.tgi-sci.com>http://www.tgi-sci.com
> >> > > > > > > > >------------------------------------------------------
> >> > > > > > > > >
> >> > > > > > > > >
> >> > > > > > > > >
> >> > > > > > > > >
> >> > > > > > > > >-------Original Message-------
> >> > > > > > > > > > From: Kenneth W. Egan <kegan@xxxxxxxxxxxxx>
> >> > > > > > > > > > Subject: RE: [SI-LIST] Re: termination for routing
> 8 SDRAMs
> >> > > > > to single
> >> > > > > > > > > Processor
> >> > > > > > > > > > Sent: Aug 11 '05 05:21
> >> > > > > > > > > >
> >> > > > > > > > > > The question might not be one of stability, but
> one of
> >> > > > > > > reliability in the
> >> > > > > > > > > > long term. Sure, you'll probably meet setup and
> hold
> >> > > to/from the
> >> > > > > > > SDRAM.
> >> > > > > > > > > > However, SDRAM typically has some pretty hot
> drivers (that
> >> > > > > I've seen,
> >> > > > > > > > > > simulated and measured in circuit ) and the real
> issue
> >> > > is over
> >> > > > > > > stressing
> >> > > > > > > > > > The input protection on the receiver, i.e.
> overshoot
> >> > > issues.
> >> > > > > > > > > >
> >> > > > > > > > > > Failure modes in this case may not occur until much
> >> > > later in
> >> > > > > time.
> >> > > > > > > > > >
> >> > > > > > > > > > KWE
> >> > > > > > > > > >
> >> > > > > > > > > >
> >> > > > > > > > > > -----Original Message-----
> >> > > > > > > > > > From: si-list-bounce@xxxxxxxxxxxxx
> >> > > > > > > > >
> >> > >
> [<mailto:si-list-bounce@xxxxxxxxxxxxx>mailto:si-list-bounce@xxxxxxxxxxxxx] On
> >> > > > > > > > > > Behalf Of Dimiter Popoff
> >> > > > > > > > > > Sent: Wednesday, August 10, 2005 8:00 PM
> >> > > > > > > > > > To: aavinda12@xxxxxxxxx; si-list@xxxxxxxxxxxxx
> >> > > > > > > > > > Subject: [SI-LIST] Re: termination for routing 8
> SDRAMs to
> >> > > > > single
> >> > > > > > > > > Processor
> >> > > > > > > > > >
> >> > > > > > > > > > I have rooted 8 x8 SDRAMs to an 8240 without any
> >> > > > > terminations and it
> >> > > > > > > > > worked
> >> > > > > > > > > > remarkably stable. However, I had 64 data bits
> rather
> >> > > than 32.
> >> > > > > > > > > > I had put 4 SDRAM chips on top and 4 on the bottom
> of
> >> > > the board,
> >> > > > > > > > > practically
> >> > > > > > > > > > next to the CPU, no connectors between.
> >> > > > > > > > > >
> >> > > > > > > > > > Dimiter
> >> > > > > > > > > >
> >> > > > > > > > >
> > ------------------------------------------------------
> >> > > > > > > > > > Dimiter Popoff Transgalactic
> Instruments
> >> > > > > > > > > >
> >> > > > > > > > > > <http://www.tgi-sci.com>http://www.tgi-sci.com
> >> > > > > > > > >
> > ------------------------------------------------------
> >> > > > > > > > > >
> >> > > > > > > > > >
> >> > > > > > > > > >
> >> > > > > > > > > >
> >> > > > > > > > > > -------Original Message-------
> >> > > > > > > > > > > From: Aravnda G <aavinda12@xxxxxxxxx>
> >> > > > > > > > > > > Subject: [SI-LIST] termination for routing 8
> SDRAMs
> >> > > to single
> >> > > > > > > > > > > Processor
> >> > > > > > > > > > > Sent: Aug 11 '05 03:29
> >> > > > > > > > > > >
> >> > > > > > > > > > > Hi All,
> >> > > > > > > > > > > I am working with a micro-processor conneted to
> 8
> >> > > SDRAM with
> >> > > > > > > 12 address
> >> > > > > > > > > > lines to all SDRAMs and 32 data lines each to two
> sets
> >> > > of four
> >> > > > > > > SDRAMs.
> >> > > > > > > > > I was
> >> > > > > > > > > > wondering if anyone has managed to route this sort
> of
> >> > > topology
> >> > > > > > > without
> >> > > > > > > > > using
> >> > > > > > > > > > terminations. If so please send information on
> topology
> >> > > > > used. The
> >> > > > > > > IO are
> >> > > > > > > > > > lvttl compatible at 3.3V. Any input on routing
> >> > > possibilities is
> >> > > > > > > welcome.
> >> > > > > > > > > > >
> >> > > > > > > > > > > Thanks & Regards,
> >> > > > > > > > > > > Alex.
> >> > > > > > > > > > >
> >> > > > > > > > > > > ---------------------------------
> >> > > > > > > > > > > Yahoo! Mail
> >> > > > > > > > > > > Stay connected, organized, and protected. Take
> the tour
> >> > > > > > > > > > >
> >> > > > > > > > > > >
> >> > > > >
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> >> >
> >> -------Original Message-------
> >>
> >>
> >>
> >-------Original Message-------
> >------------------------------------------------------------------
> >To unsubscribe from si-list:
> >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >
> >or to administer your membership from a web page, go to:
> >//www.freelists.org/webpage/si-list
> >
> >For help:
> >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> >List FAQ wiki page is located at:
> > http://si-list.org/wiki/wiki.pl?Si-List_FAQ
> >
> >List technical documents are available at:
> > http://www.si-list.org
> >
> >List archives are viewable at:
> > //www.freelists.org/archives/si-list
> >or at our remote archives:
> > http://groups.yahoo.com/group/si-list/messages
> >Old (prior to June 6, 2001) list archives are viewable at:
> > http://www.qsl.net/wb6tpu
> >
> >
> >
> >
> >
>
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> //www.freelists.org/webpage/si-list
>
> For help:
> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
> List FAQ wiki page is located at:
> http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>
> List technical documents are available at:
> http://www.si-list.org
>
> List archives are viewable at:
> //www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
-------Original Message-------
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
