[SI-LIST] Re: termination for routing 8 SDRAMs to single Processor
- From: "HreidmarKailen" <HreidmarKailen@xxxxxxxxxxx>
- To: <Chris.Cheng@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 11 Aug 2005 02:00:11 -0700
> Mama says you can't learn if you don't do your homework and just ask
> your teacher for an answer.
Geez, is it that time of the month for Mama?
:-)
PS: I will stand justly rebuked if I have offended anyone.
----- Original Message -----
From: "Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Wednesday, August 10, 2005 7:35 PM
Subject: [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor
> Mama says you can't learn if you don't do your homework and just ask =
> your teacher for an answer.
> That said, our first generation systems do have 8 stacked registered =
> DIMMs sitting on a riser card with connector to our ASIC at full 133MHz =
> SDRAM speed. They are organized as two banks of 4 stacked DIMMs each.
> So the loading is 1 riser connector, 4x DIMM connector, stub on DIMM, =
> 8xSDRAM loads and about 12 inches of trace. No terminator.
> The key is take advantage of the fact that :
> a) Address/control lines are unidirectional
> b) data is semi-unidirectional.=20
> When DIMM is driving, you only need to make the memory controller input =
> timing.
> When the memory controller is driving, if you make the signal arrive =
> "almost" the same time to each DIMM, you've make your timing.
> What makes things interesting is when you start depopulating DIMM's on =
> the riser card.
> It will help if you design your own memory controller like me also.
> HTH
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Aravnda G
> Sent: Wednesday, August 10, 2005 5:29 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] termination for routing 8 SDRAMs to single Processor
>
>
> Hi All,
> I am working with a micro-processor conneted to 8 SDRAM with 12 address =
> lines to all SDRAMs and 32 data lines each to two sets of four SDRAMs. I =
> was wondering if anyone has managed to route this sort of topology =
> without using terminations. If so please send information on topology =
> used. The IO are lvttl compatible at 3.3V. Any input on routing =
> possibilities is welcome.
> =20
> Thanks & Regards,
> Alex.
> =09
> ---------------------------------
> Yahoo! Mail
> Stay connected, organized, and protected. Take the tour
>
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