[SI-LIST] termination for routing 8 SDRAMs to single Processor
- From: Aravnda G <aavinda12@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 10 Aug 2005 17:29:05 -0700 (PDT)
Hi All,
I am working with a micro-processor conneted to 8 SDRAM with 12 address lines
to all SDRAMs and 32 data lines each to two sets of four SDRAMs. I was
wondering if anyone has managed to route this sort of topology without using
terminations. If so please send information on topology used. The IO are lvttl
compatible at 3.3V. Any input on routing possibilities is welcome.
Thanks & Regards,
Alex.
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