Chris- I just treated the cap as a lumped element with .1uF capacitance, 1nH series inductance, .1 ohm series resistance. I used 13 mil vias, spaced 130 mils as if it were about a usual 0603 type placement with no special techniques to reduce loop area of the mounting. Properly, I realize it would be more accurate to do this more carefully by including pads and such, but I didn't spend the time to do that for this exercise. (there's only so many hours in the day.) Certainly all of those parameters of the cap can be varied. I just wanted to see the basic effect of the location, then thought I would share what I had here. If you or anyone else wants to take my simulation files as a starting point and add more details, by all means please do! and please share! I would be interested to see the result. Like I say, more simulation monkeys banging on more computers might give us some more useful knowledge. Or suggest some idea and maybe I'll give it a try later. kim At 05:10 PM 8/13/2003, Chris Cheng wrote: >Kim, >Just curious, what kind of via and pad structure did you used to connect the >bypass caps to the planes (in particular to the 50 mil planes) ? > > -----Original Message----- >From: Kim Flint [mailto:si@xxxxxxxxxxxx] >Sent: Wednesday, August 13, 2003 3:59 PM >To: si-list@xxxxxxxxxxxxx >Subject: [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator > >At 08:26 AM 8/11/2003, Lee Ritchey wrote: > >If the location of decoupling capacitors matters, perhaps some technical > >demonstration would prove that. Short of such a demonstration, this is > >speculation and not the sort of thing that should be used to make design > >choices. > >In light of Lee's request for more analysis and less opinion, I thought I >might try doing a few simulations to see what effect due to capacitor >location could be shown. I mainly looked into layer switching and the >effect of cap placement on resulting power fluctuations. I used Sigrity's >Speed2000 demo version, so other people can take my files and easily >experiment with them as they like even if they don't own a copy. The demo >version is free and limited in functionality, but useful for small test >cases like this. You can get it from Sigrity's web site, >http://www.sigrity.com. I put the simulation files, some explanation about >them, and some interesting plots on my website, where you are welcome to >grab them: > >http://www.kimflint.com/capplacement/capplacement.html > >I think there are at least two aspects to this issue of capacitor placement >to consider, and they both appear to be mixed together in the discussion so >far. One is the impedance of the PDS with frequency and whether capacitor >placement affects it, especially considering I/O behavior on the die. This >is important in determining whether voltage margins will be maintained when >current is switched by a transistor on our die at a given frequency. We >want to analyze whether we get SSO problems and such due to supply collapse >and where we might place capacitors usefully to help. That much I think has >been covered already. > >A second aspect might be called "return current control", which I would >like to discuss some more. A few people noted that they believe capacitor >placement affects EMI, or loop currents. Probably we should include >crosstalk in there as well, since a large loop current on an aggressor >return path can result in crosstalk to victim nets. Capacitors are often >placed in strategic locations on a board to control such problems, by >providing a path for the return current to switch layers. For example, we >might place caps at locations where traces switch across layers, cross >plane splits, or escape packages. So does that work? Or more usefully, when >does the cap location matter and when does it not matter? How much effect >does it have? > >In an ideal case, all of our signals would have a perfectly continuous >transmission line environment from start to finish. Practically however, >this is rarely the case in real board designs. For example, as a signal >transitions from the package to the board, it may end up with different >reference planes on the PCB than it had on the package. It may be necessary >to do this briefly for a BGA escape, or because we simply don't have any >information about the package routing of another vendor's BGA and we don't >know what reference planes to use. Or, in a dense board we may be forced to >switch layers on some signals due to routing congestion. Of course we all >try to minimize this, but it's gonna happen. We know that return currents >travel on the reference plane following our trace, and wherever we switch >layers the return current has to find a way to switch reference planes >along with it. If there is no convenient place for the return current to >transition to the new reference planes, we may end up with a large current >loop. This radiates and causes crosstalk, EMI, noise, etc. We use >capacitors to make an ac path across the planes and hopefully limit the >loop area. > >It is really interesting to run the simulations and see the 3d animation of >the planes with the wave propagating as the signal switches layers. It >looks like a pebble dropping in a pond, with the waves rippling out from >the via where the layer switch happens. It gives you an intuitive idea of >what happens on your planes when you switch layers, so I encourage you to >take my files and try the simulation yourself if you haven't done this >before. > >The simulations I did tend to lend credence to the idea that you shouldn't >rely on rules of thumb or absolute statements. You need to consider your >application! And simulate! Because from what I interpret from the results, >sometimes the cap locations matter and sometimes they don't. It is no more >correct to say "location never matters" then it is to say "location always >matters." > >In my simulations I compared closely spaced planes vs. widely spaced >planes, different cap positions, and different plane sizes. I used a signal >pulse with 100ps edge rates, so the frequency content is fairly high. In >cases where the plane spacing is close (3mil) and the interplane >capacitance relatively high, the cap location did not matter too much. >However, when the plane spacing was larger (50mil) and therefore less >natural interplane capacitance, the bypass cap location did make a >difference even with 100ps edge rate signals. Clearly though, improving >interplane capacitance had a much better result, reducing peak voltage >fluctuations on the planes by an order of magnitude in this case. So, in >cases where you can't get much interplane capacitance due to stackup >limitations, small area power islands, or switching across multiple layers, >cap location might make a difference for you even at fairly high >frequencies. In other cases where you are switching across closely spaced >planes, it probably doesn't matter. > >Again, I would urge you to try it yourself and use your imagination to come >up with your own conditions. Feel free to use my files as a starting point. >I'm just one simulation monkey banging on one computer, and there are many >variables I didn't try. (different edge rates, different capacitor >parasitics and mounting techniques, more caps, etc.) A few more monkeys >providing their results could give us all a lot more knowledge. also, >comments welcome! If you spot some error in what I did, let me know. > >thanks, >kim > > > >------------------------------------------------------------------ >To unsubscribe from si-list: >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field > >or to administer your membership from a web page, go to: >//www.freelists.org/webpage/si-list > >For help: >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field > >List archives are viewable at: > //www.freelists.org/archives/si-list >or at our remote archives: > http://groups.yahoo.com/group/si-list/messages >Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu > ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu