[SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator

  • From: "Peter Arnold" <parnold@xxxxxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Mon, 11 Aug 2003 14:59:44 -0700

All,

I am not sure there should be so much controversy over this placement thing.
Among the conclusion in the UMR paper that I have a copy of [1] is this
assertion: "...all decoupling capacitors are shared in the frequency range
where they are effective (typically below 200-300MHz), and the location of a
decoupling capcitor on the board is relatively unimportant."

The "unimportant placement" claim is made dependent on the condition that
the caps, as mounted, are ineffective above 200MHz. At this frequency an
8"x9" test board is electrically small with respect to 200MHz wavelength in
FR4 (30") and the paper reports placement not to be crucial in determining
impedance.

I think this electrical-smallness, and taking capacitor mounting inductance
at 2-10nH to be >> plane inductance between parts, is what prompts them to
simplify the power delivery model to a network connected between two spice
nodes as if all components were physically at the same place. Analyzing this
the authors identify a frequency "fa" lying between the last zero and the
last pole of the impedance plot above which the decouplers are ineffective.
If this frequency is low as in the examples given, then cap placement might
well not matter.

But designs today do not necessarily support the simplification given above.
Modern techniques like via-in-pad, multiple fanouts, "broadside" case
connections etc. reduce mounted inductance to 1nH or less per part. This
should allow mounted capacitors to be effective at higher frequencies where
wavelengths are only a few inches and the board is no longer electrically
small. At this point the everything-between-two-nodes and
no-inductance-in-series-with-plane-capacitance simplification may not hold
and a bedspring-type model would be needed. Decoupler placement may then
become important (as experience appears to confirm!) This does not
contradict the UMR authors' statement, which relates to a
high-mounted-inductance regime and frequencies below 200MHz on a small
board.

Can anyone comment?

[1] Hubing et al., "Power Bus decoupling on Multilayer Printed Circuit
Boards," in IEEE trans. EMC vol 37, no. 2, May 1995.

Regards,
peter arnold.




-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ray Anderson
Sent: Monday, August 11, 2003 9:36 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator




Lee Ritchey wrote:
> If the location of decoupling capacitors matters, perhaps some technical
> demonstration would prove that.  Short of such a demonstration, this is
> speculation and not the sort of thing that should be used to make design
> choices.
>
> It's time to do some good engineering on this subject and do away with
> opinion.  The UMR paper is good engineering.  Anyone who chooses to
> disagree with it has the burden of showing where it is wrong by using some
> good science.
>
> Lee
>
> Lee Ritchey
> leeritchey@xxxxxxxxxxxxx
> Why Wait?  Move to EarthLink.


Or conversely, show that it doesn't matter.

Take a large system board (say about 24" square) put a bunch of high current
processors and ASICS on the left side of the board. Put all your decaps
on the right side of the board (since you maintain position doesn't matter).

In this hypothetical case I can just about guarantee the board won't
function
properly or pass EMI. Admittedly, it is a contrived case, but I think it
illustrates the point.

As far as the technical demonstration goes, we have indeed demonstrated to
ourselves that position does matter.

I'm not attempting to further an argument, but I do feel those who have
responded with  viewpoints other than yours shouldn't be chastised and
accused
of spreading unfounded opinion. Don't discount the chance that an opinion
that
differs from yours just might be correct.

-Ray Anderson
Sun Microsystems Inc.

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