[SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator

  • From: Ray Anderson <Raymond.Anderson@xxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Fri, 1 Aug 2003 12:50:10 -0700 (PDT)

With all due respect to the UMR authors, I think the location
of a decap on a set of power planes DOES matter.

There is an inherent time delay associated with the current flow
from the location where a decap is placed to the location where the 
chip to bypassed is located.

The decaps job is to provide current to the load quickly enough
that a voltage collapse on the planes doesn't occur. If the decap
is too far away from the current consuming load it is possible
that load's need for a pulse of current will be over before the 
current can get there.

At low frequencies you can place a decap just about anywhere on a plane
and it will function just fine. At higher frequencies the decap must
be closer to the device to be bypassed. The concept of "effective bypassing
radius" says that a decap must be within say 1/6 to 1/10 wavelength
at the frequency of interest to be effective. (the exact number is
debatable). The frequency of interest is the resonant frequency of
the mounted decap (where the caps ESR is lowest), and the distance is 
a function of the speed of propagation with a given dielectric between
the planes (around 180ps/inch for FR4).

You need to consider the role each component of a PDS (power distribution
system) plays in maintaining a low impedance across a wide bandwidth.
A typical PDS is composed of a VRM, bulk capacitors, ceramic decaps, and
the power planes and last but not least the package housing the silicon.

The VRM provides a low impedance from DC to perhaps a few hundred kHz,
the bulk capacitors contribute their impedance profile from a few 
hundred kHz up to about a MHz. From a Mhz to maybe 120MHz or so the
ceramic decoupling caps provide low impedance. Above that frequency
the distributed capacitance provided by the planes provides the requisite
low impedance to the PDS. When the individual impedance profiles of
each of the constituent parts are superimposed, the resulting composite
profile provides a low impedance over the full frequency range that the
PDS was designed for. Note that above the package resonance frequency
(which usually is from about 50 to 100 MHz for typical packages) decoupling
on the board is ineffective and the necessary decoupling must be provided
for either in the package or on the silicon. However, at frequencies
above the package resonance frequency the discrete decaps and distributed
plane capacitance can be most useful for EMI purposes.

To summarize, at low frequencies, the decoupling capacitors can be placed
almost anywhere withing reason and will be effective. As the frequency
of interest increases, the allowable distance decreases. As an example,
at 1 MHz the wavelength (on FR4) is around 214 meters. So lambda/10 is
around 21 meters. Hence, if your decap which is effective at 1 MHz is
within 21 meters of the consuming device, then the decoupling will be
effective. Conversely, if you are trying to decouple at device with
a decap that is effective at say 100 MHz then the wavelength of interest
is about 1.4 meters. Lambda/10 is then .14 meters (approx 5.5 inches).
In this case if the decap is appreciably more than 5.5 inches from the
currewnt consumer then the delay will be such that the decap will not be able 
to 
provide current quickly enough to be effective.

-Ray Anderson
Sun Microsystems Inc.


Lee Ritchey wrote: 
>> If you remember the UMR paper on power bus decoupling, it made a clear case
>> that the location of the capacitors is relatively unimportant.


Abe Riazi wrote: 
>To be fair, it should be added that different recommendations ( from above) 
exist in literature
>regarding optimum location of the decoupling caps.
>
>Two examples follow:
>
>1.  Stephen H.Hall et al., " High-Speed Digital System Design........", on 
>page 
247 it is stated:
>
>" Figure 10.10 suggests not only that the local decoupling capacitor value 
should be chosen
>appropriately but that the capacitor is placed physically close to the 
component to minimize
>the loop area ".
>
>2. A technical paper by R. Chen, "Where to Place Decoupling Capacitors?..."  
available on
>www.sigrity.com web site, implies that the best location for decoupling caps 
needs to
>be ascertained with aid of electromagnetic field simulation.
>
>Best Regards,
>
>Abe Riazi
>ServerWorks

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