[SI-LIST] Re: Article discussion on bad packages
- From: Ray Anderson <ray.anderson@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 30 Dec 2004 10:43:40 -0800
Chris Cheng wrote:
>Istvan,
>
>I would also like to ask the questions for one last time :
>a) Does SUN use IBIS or SPICE to analyze its critical IO or CPU core power
>distribution ?
>b) Were you actually responsible to work on the CPU core power distribution
>analysis for your company ?
>I will be waiting till hell freezes over.
>
>
>
One way I've done core PDN simulations on processors in the past was to
initially have the silicon design guys run time domain transistor level
core simulations. These involved millions of transistor and took way too
long to run. From the time domain I vs T results of those simulations a
behavioral model consisting of PWL current sources or PWL voltage
controlled resistances was developed. We then utilized those behavioral
models to characterize the time domain response of the core PDN's. It
was always instructive to look at the p-p current excursions at the
silicon, at various points in the package and finally at the PCB level
to visualize the effects of the on chip, on package and PCB level
decoupling networks. The behavioral models ran in seconds or minutes as
compared to the transistor level models they were derived from which
executed in terms of days or weeks.
-Ray Anderson
Senior Signal Integrity Staff Engineer
Xilinx Inc.
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