[SI-LIST] Re: Article discussion on bad packages
- From: "Rotem Gazit" <rotemg@xxxxxxxxxxxx>
- To: <scott@xxxxxxxxxxxxx>, "silist" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 21 Dec 2004 09:01:25 +0200
=20
This article lists some of painful issues that are well known to all
dealing with high-speed IC packaging.=20
I would like to add to the obstacles listed in the article the lack of
high speed oriented substrate layout designers and awareness for
high-speed requirements and design methodology among substrate vendors.
This situation is much painful for fables IC vendors who usually rely on
the substrate vendors for the substrate layout.
One point I disagree with the information given in the article is the
availability of "good" EDA simulation tools.
As far as my experience goes the only available option is using high end
RF simulators like Ansoft HFSS which also needs lots of tweaking before
being able to import correctly a routed database. I've spend few week
with the new Cadence 15.2 integrated 3D modeler - couldn't get any
useful result. So did the Cadence the application engineer :-[ .
Rotem Gazit
Director of System & Product Engineering.
Mysticom Semiconductor Ltd.
Tel: +972 9 8636424
Fax: +972 9 8636466
1 Hazoran St, Netanya 42504, Israel.
www.mysticom.com
=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Scott McMorrow
Sent: Monday, December 20, 2004 10:27 PM
To: silist
Subject: [SI-LIST] Article discussion on bad packages
I'd be interested in peoples thoughts about the following article from
today's EE Times.
http://www.eedesign.com/article/showArticle.jhtml?articleId=3D55801038
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=20
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