[SI-LIST] Re: Article discussion on bad packages
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: hassan@xxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Tue, 21 Dec 2004 18:45:03 -0500
Hassan
I did focus on the PDS becuase of a similar focus in the article:
" The design called for FPGAs with integrated serdes capability to
be used as serial links. But test data showed severe ground bounce
and power bounce on the board, as well as performance problems
related to the operation of the serdes links in the system environment."
" Zaszio sited several FPGA packaging problems. These include
inductance on the power supply plane, poor assignment of power and
ground pins goint to the pcb and pour decoupling inside the package
for hihg-speed current spikes. I/Os do not use controlled-impedance
transmission lines, and unless power and ground are assigned with
low-inductance connections, it's easy to end up with simultaneous
switching noise and false signals, he said."
But similar remarks apply to the remainder of the package design. I
have worked with many packages, from all the major vendors of FPGAs,
ASICs and commercial off the shelf chipsets, that have had severe
impedance control and crosstalk problems. I do not worry much about the
impedance control issues. But the crosstalk issues can be killer. If
you've read many of my postings on this list, you'll remember my
discussions of reflected reverse crosstalk on devices with low impedance
unterminated drivers. Fortunately, crosstalk is one of the easiest
things to characterize by measurement with a TDR.
Crosstalk, PDS noise, and PDS impedanced can all be characterized by a
user with the right tools and test setup. (yes, even part of the
package PDS can be measured. All one needs are a TDR, a VNA and a
clever test board design. With these and some well designed FPGA test
code we can perform the evaluation necessary for informed design decisions.
As Steve has just stated, we just need to perform the measurements
necessary to ensure the noise levels required by the manufacturer at the
package/pcb boundary. But, if we do want to delve further, the
information is there for the measuring.
regards,
scott
Hassan O. Ali wrote:
>On Dec 21, Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:
>
>
>>"It's the inductance stupid" should be our mantra. Or better yet, "It's
>>the PDS Impedance Stupid,", which Larry, Ray and Istvan have been saying
>>for years.
>>
>>
>
>Scott,
>
>The article and the mantra you advocate seem to suggest that high-speed
>package SI woes
>are all (or for the most part) related to PDS impedance. I don't believe that
>is
>correct. You can have a perfect PDS at the package level and still suffer
>high-speed SI
>problems due to other aspects of package design. And of course all that is
>widely known,
>I'm just afraid that your statements may be misconstrued (probably I've just
>done that :-
>)).
>
>I've seen packages with very poor impedance and crosstalk control on their
>high-speed
>nets. Huge packages like those for FPGA's are extremely challenging to route
>in a manner
>that ensures good impedance and crosstalk control. As a results, those
>packages suffer
>from severe signal reflection and crosstalk problems even with perfect PDS. Of
>course,
>poor PDS design exacerbates the problem.
>
>
>
>>If a package is "broken" due to high PDS inductance, then
>>it can never work above a particular operating dI/dt current profile.
>>We agree that this is not well characterized by component vendors.
>>However, it can be measured and characterized by users.
>>
>>
>
>If by "this" you meant the package PDS inductance (not the dI/dt), then I
>think it is
>not easy for ordinary users to measure it. Assuming characterizing a bare
>package
>substrate (without the die), a user must have a VNA with appropriate probes
>and
>calibration kits for the bump-side and ball-side measurement. Moreover, a
>typical FPGA
>package has 10's of power and ground bumps and balls which would be difficult
>to probe
>and measure at the same time. The best you can get with a typical VNA is the
>impedance
>of a few power and ground pins (not more than 4) measured with remaining
>bumps/balls
>either shorted somehow or left open. The PDS impedance measured this way may
>not be
>representative of the PDS impedance seen by all the high-speed signals of a
>packaged
>device mounted on a PCB.
>
>Best regards.
>
>Hassan.
>
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Scott McMorrow
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