[SI-LIST] Simulation Problem

  • From: "manish bhakuni" <silverhawk2040@xxxxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: 30 Dec 2004 19:36:11 -0000

Dear Sir/Mam
       How do i tackle problems of "negative mos conductance" and "internal 
time step too small for transient analysis" while simulating prelayout and post 
layout modules of my Multiplier.
       Plz also help me in Radix-16 Booth Encoding for my multiplier
Manish Bhakuni
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