[SI-LIST] Re: Article discussion on bad packages
- From: "Hassan O. Ali" <hassan@xxxxxxxx>
- To: silist <si-list@xxxxxxxxxxxxx>
- Date: Tue, 21 Dec 2004 18:21:59 -0500 (EST)
On Dec 21, Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:
>
> "It's the inductance stupid" should be our mantra. Or better yet, "It's
> the PDS Impedance Stupid,", which Larry, Ray and Istvan have been saying
> for years.
Scott,
The article and the mantra you advocate seem to suggest that high-speed package
SI woes
are all (or for the most part) related to PDS impedance. I don't believe that
is
correct. You can have a perfect PDS at the package level and still suffer
high-speed SI
problems due to other aspects of package design. And of course all that is
widely known,
I'm just afraid that your statements may be misconstrued (probably I've just
done that :-
)).
I've seen packages with very poor impedance and crosstalk control on their
high-speed
nets. Huge packages like those for FPGA's are extremely challenging to route in
a manner
that ensures good impedance and crosstalk control. As a results, those packages
suffer
from severe signal reflection and crosstalk problems even with perfect PDS. Of
course,
poor PDS design exacerbates the problem.
> If a package is "broken" due to high PDS inductance, then
> it can never work above a particular operating dI/dt current profile.
> We agree that this is not well characterized by component vendors.
> However, it can be measured and characterized by users.
If by "this" you meant the package PDS inductance (not the dI/dt), then I think
it is
not easy for ordinary users to measure it. Assuming characterizing a bare
package
substrate (without the die), a user must have a VNA with appropriate probes and
calibration kits for the bump-side and ball-side measurement. Moreover, a
typical FPGA
package has 10's of power and ground bumps and balls which would be difficult
to probe
and measure at the same time. The best you can get with a typical VNA is the
impedance
of a few power and ground pins (not more than 4) measured with remaining
bumps/balls
either shorted somehow or left open. The PDS impedance measured this way may
not be
representative of the PDS impedance seen by all the high-speed signals of a
packaged
device mounted on a PCB.
Best regards.
Hassan.
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
