[SI-LIST] Re: Article discussion on bad packages

  • From: "Peterson, James F (FL51)" <james.f.peterson@xxxxxxxxxxxxx>
  • To: silist <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 21 Dec 2004 11:48:42 -0700

Scott,

Your response below is a fair description of the issue and this is one of
the silist threads I'll be tracking. 

I also thought the EETimes article was way too high level to be of any use
and I'm looking forward to all of the grisly details in Weir's DesignCon
paper. 

I'm in the process of implementing a high speed bus that is 144 databits
wide into an FPGA and I'm a little apprehensive about just following the
rules in their ground bounce guidelines.

Regards,
Jim

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Scott McMorrow
Sent: Tuesday, December 21, 2004 1:14 PM
To: silist
Cc: steve@xxxxxxxxxxxxx; Dr. Edward P. Sayre; MikonCons@xxxxxxx
Subject: [SI-LIST] Re: Article discussion on bad packages

All,
My purpose for this question was multi-fold:

1) To establish some constructive feedback and solutions
2) To establish the fallacies (and truths) in the article.
3) To encourage a public discussion on package power delivery issues (yet
again), and specifically those issues concerning FPGA design.
4) To see if there are others out there who are successfully using FPGAs in
their high-performance designs (we expect there are quite a few.)

As you all may or may not know, Steve Weir and I have collaborated in the
study of PCB bypass strategies, capacitor inductance modeling and
measurement (both mounted and unmounted), PDS design and FPGA power
delivery.  Of course we stand on the shoulders of the work done by Larry,
Ray and Istvan.  We think that we understand the issues and challenges of
FPGA power delivery and design pretty well and we think that we can add to
the scientific knowledge in this area.  In that light, Steve has authored a
paper to be presented in the upcoming DesignCon 2005, " High Performance
FPGA Bypass Filter Networks."

We have found that once a bit of physics and science is applied to this
problem, many of the "doomsday scenarios" proclaimed are in fact the result
of sub optimally engineered systems.  It is very easy to "blame the package"
for problems that may be PCB design problems.  It is equally easy to "blame
the PCB designer" for problems that may be silicon or package design
problems.  FPGA designs are a "target rich environment" for criticism
because of their inherent general purpose and high performance nature.  Not
every engineer has the opportunity to design their own custom IC.  But any
engineer (reading between the lines is authorized) can design a unique FPGA
into system.  A custom chip design should always have better performance
than an FPGA.  This is not unexpected or new news. What is unreasonable is
the attitude that "they" 
(whoever they might be) should have done my PDS engineering and design
tradeoffs for me.

"It's the inductance stupid" should be our mantra.  Or better yet, "It's the
PDS Impedance Stupid,", which Larry, Ray and Istvan have been saying for
years. Yes, FPGA packages do have finite power/ground inductance. 
This happens to be the nature of all physical electrical objects larger than
a point.  If a package is "broken" due to high PDS inductance, then it can
never work above a particular operating dI/dt current profile.  
We agree that this is not well characterized by component vendors.  
However, it can be measured and characterized by users.   Equally, we 
can say that for any device to operate reliably it must have a total PDS
impedance below some threshold target across some frequency range.  The
impedance target and frequency range is rarely (if ever) specified.  
However, it can be measured by the user. 

As I have been saying for years, you cannot improve the performance of a
package with your PCB PDS design, but you can make it much, much worse.  
Having been involved in the design and robust analysis of quite a few
packages and systems I can say that there are a few packages that are
terminally ill, but generally that is not the case.  Most are a good
compromise between cost and performance.

 In many designs, root cause for FPGA failures can be traced to one of the
following:

    * Too many simultaneous switching IOs within a package power
      delivery group, or a mixture of dissimilar busses within one power
      group.
    * Poor bypass capacitor selection and/or placement.
    * Poor bypass capacitor to plane attachment.
    * Poor PCB stackup design.
    * Poor device placement on the PCB.

Ultimately this reduces to either extraordinary localized dI/dT, which is an
IO assignment, analysis and architecture issue, and/or high PDS impedance.

" The sky is not falling." 

These are problems of physics which can be resolved with detailed
engineering analysis, and without finger pointing.  If anyone is interested,
we (and our colleagues) have many customers that are successfully using FPGA
devices from multiple vendors in mission critical designs every day.  We
have even been known to pick up the pieces in designs where others have only
failed.


best regards,

scott

--
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
(503) 750-6481 Cellular
http://www.teraspeed.com

Teraspeed is the registered service mark of Teraspeed Consulting Group LLC



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