Giancarlo, Rotem's remark on Ansoft HFSS is correct. You always have your fingers crossed when you import Cadence package databases into HFSS. In my experience, most of the time I have to make painful geometrical tweaking to help HFSS successfully mesh the problem. I'm particularly annoyed by 10's or even 100's of model, contact, and proximity errors that show up almost every time I model a package using HFSS. Even as I speak I have a model that has failed to mesh and the Meshmaker has reported 699 errors!! The software simply gets severely challenged if the model has very short edges in close proximity to long edges which is a given for many high-speed packages. I wish there was away to instruct HFSS to automatically eliminate all very small edges that have negligible EM effects. The meshing program also has to be improved to suit package environments which is drastically different from simple waveguide, transmission line, and antenna model environments that HFSS has already perfected. Best regards. Hassan. On Dec 22, "giancarlo guida" <gguida@xxxxxxxxxx> wrote: > > Dear Sir, > I am really surprised about your bad experience with the interface > between Cadence and Ansoft. > > I personally support this interface working on Ansoft side > I personally support customer like ST and MICRON, IBM and they are able to > import their > design in our tools. > > At the moment we have several interface with EDA tool > including APD, Allegro Virtuoso, Synopsis Mentor Zuken > > If you are not getting good results with the traslation > I would suggest you to contact directly the Ansoft support engineer > to fix your problem > > Giancarlo > > ----- Original Message ----- > From: "Rotem Gazit" <rotemg@xxxxxxxxxxxx> > To: <scott@xxxxxxxxxxxxx>; "silist" <si-list@xxxxxxxxxxxxx> > Sent: Tuesday, December 21, 2004 8:01 AM > Subject: [SI-LIST] Re: Article discussion on bad packages > > > =20 > This article lists some of painful issues that are well known to all > dealing with high-speed IC packaging.=20 > I would like to add to the obstacles listed in the article the lack of > high speed oriented substrate layout designers and awareness for > high-speed requirements and design methodology among substrate vendors. > This situation is much painful for fables IC vendors who usually rely on > the substrate vendors for the substrate layout. > > One point I disagree with the information given in the article is the > availability of "good" EDA simulation tools. > As far as my experience goes the only available option is using high end > RF simulators like Ansoft HFSS which also needs lots of tweaking before > being able to import correctly a routed database. I've spend few week > with the new Cadence 15.2 integrated 3D modeler - couldn't get any > useful result. So did the Cadence the application engineer :-[ . > > > Rotem Gazit > Director of System & Product Engineering. > Mysticom Semiconductor Ltd. > Tel: +972 9 8636424 > Fax: +972 9 8636466 > 1 Hazoran St, Netanya 42504, Israel. > www.mysticom.com > > =20 > > > -----Original Message----- > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] > On Behalf Of Scott McMorrow > Sent: Monday, December 20, 2004 10:27 PM > To: silist > Subject: [SI-LIST] Article discussion on bad packages > > I'd be interested in peoples thoughts about the following article from > today's EE Times. > ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu