[SI-LIST] Re: Jitter transfer vs. accumulation
- From: "Tang, George" <George.Tang@xxxxxxx>
- To: <Istvan.Novak@xxxxxxx>
- Date: Fri, 23 Mar 2007 12:53:33 -0600
Hello Istvan,=20
Yes, we have a specification of VDD +/- 5%, but the chips are designed
and simulated to VDD +/- 10%, just to give ourselves (and the customers)
some margin. =20
Thanks,=20
=20
George=20
=20
Note: Effective October 14, 2006, My LSI Logic Email address will change
to: george.tang@xxxxxxx
Please update address books and email lists accordingly.
-----Original Message-----
From: Istvan.Novak@xxxxxxx [mailto:Istvan.Novak@xxxxxxx]=20
Sent: Friday, March 23, 2007 4:46 AM
To: Tang, George
Cc: Alfred P. Neves; weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Jitter transfer vs. accumulation
George,
I have been following with great interest the discussion on jitter.=20
I need to admit that I did my PhD on stochastic processes in
precision measurements many years ago, so my math has become
rusty. For this reason I will leave the details to those who practice
them today.=20
However, I have a question to you about the applications. If I am
not mistaken, in your arguments you assume that the power going
to the VCO and PLL circuit is clean, or at least clean enough that
power-supply modulation can be neglected. Does this mean that
for chips that you design the customers get a specification regarding
how clean the supply rail needs to be going to the analog pins?
Regards,
Istvan Novak
SUN Microsystems
Tang, George wrote:
>Alfred,=3D20
>
>See comments in [[[[[ ]]]]]. =3D20
>
>George=3D20
>
>
>-----Original Message-----
>From: Alfred P. Neves [mailto:al.neves@xxxxxxxxxxx]=3D20
>Sent: Wednesday, March 21, 2007 11:07 PM
>To: weirsi@xxxxxxxxxx; Tang, George; si-list@xxxxxxxxxxxxx
>Subject: RE: [SI-LIST] Re: Jitter transfer vs. accumulation
>
>George,
>
>
> =20
>
>>{{{{{Alfred made the initial postulate that open-loop VCO has rms=3D20
>>jitter governed by his funny equation Y=3D3DmX + b, where Y is the
rms=3D20
>>jitter, X is the time duration of measurement, and m > 0. This
shows=3D20
>>that as time goes to infinity, the rms jitter of the open-loop VCO
also
>> =20
>>
>
> =20
>
>>goes to infinity.
>> =20
>>
>
>No George, this is not what I said. It is the autocorrelation record
of
>the VCO that increases linearly on a log-log plot, where the axis are
>log(RMS jitter) and log(time interval length), where this is not to be
>confused with an RMS jitter or whether it is bounded or not. =3D20
>
>[[[[[Amazing. If your autocorrelation record for the open-loop VCO
>looks like Y=3D3DmX + b, you have either invented a random-noise-free
>environment (congratulations to you,) or your environment is so bad
that
>it is completely dominated by deterministic modulation so you cannot
>take clean measurements at all. My guess is that the latter case is
the
>truth. ]]]]]]]=3D20
>
>
>I already
>provided numerous references regarding this and can also provide
>numerous measurements for several VCO's to illustrate VCO RMS jitter
>characteristics versus measurement interval. We have used this
analysis
>100's of times for closed (and open loop) PLL analysis to determine the
>PLL loop bandwidth and peaking in the PLL loop response. =3D20
>
>[[[[[Like I said before, we do not see this problem in our
measurements.
>The VCO RMS jitter is bounded, and so is the PLL RMS jitter. The RJ
>distribution takes on a true Gaussian waveform. In addition to that,
we
>test our communication channels (including TX, RX, &PLL) for weeks with
>no errors. All our measurements fairly closely match up with the
system
>BER predicted by the model simulation. We do not see the problems that
>you are fighting with. ]]]]]=3D20
>
>
>You can also
>use this analysis to analyze jitter problems like spurious response due
>to charge pump leakage, power supply junk like switching noise or HF
>digital, XTALK in the substrate, SSO, and jitter multiplication from
PLL
>to PLL. The basis for this analysis is work by John McNeil in
>collaboration with Analog Devices in the mid 90's - have you read the
>reference already provided, I can send you a copy if need be? I
didn't
>originate the concept, just use the practical elements to analyze PLL's
>and VCO's. Before you belittle this, become dismissive, or make any
>more personally targeted comments it may behoove you to do a bit of
>homework. And once again, you are asked to significantly raise the
>level of your professionalism in your communications. =3D20
>
> =20
>
>>He further claimed that with the feedback loop of=3D20
>>the PLL, the rms jitter became bounded. You don't think Alfred =
was=3D20
>>crazy enough to make the mistake of comparing phase jitter of VCO
to=3D20
>>the RMS jitter of the PLL, do you? That will be comparing apples
to=3D20
>>bananas, let alone oranges
>> =20
>>
>
>No, I did not say this either. The reference was regarding the
>autocorrelation record, NOT any comment regarding characteristics of
VCO
>RMS jitter. A VCO has certain properties: It has poor frequency
>stability, it is temperature sensitive, it is not WSS (wide sense
>stationary), it has a LOT of low frequency jitter due to numerous 1/f
>noise sources, it also has unbounded RMS jitter, but the estimate of
the
>RMS jitter is difficult to measure since: Measure the RMS of a VCO
>over a certain time T, remeasure the RMS jitter later over the same
time
>interval and you will arrive at a different RMS number since it is not
a
>stationary process. Sample size really has little to do with this.
>BTW, do you have data on "stable" VCO's in terms of PPM frequency drift
>versus time, after you claim the temperature stabilizes in 1-2 hours.
>
>[[[[[If the RMS RJ of the VCO is unbounded, the closed-loop PLL will
>never be fully stable since the feedback has finite correction
>capability. The only way the PLL can be fully stable is that the RMS
>jitter of the VCO HAS TO BE BOUNDED. We measure the PLL for say 20
>minutes on day one and another 20 minutes on day 2 and day 3, and the
>Peak-to-Peak jitter and RMS jitter for each day matches the results of
>the other days down to 0.1ps range. To say that the VCO and/or the PLL
>has unbounded RMS jitter will be a tough tough sell, since you will
>never be able to get this kind of repeatability otherwise. ]]]]]]=3D20
>
>
>NOW, place the VCO into a PLL loop that is locked on a stable input
>signal, the VCO accumulated phase jitter is shaped by the PLL loop
>response. The RMS RJ jitter measured (using some RJ-DJ extraction)
will
>be unbounded - by definition. =3D20
>
>[[[[[Why? What equipment do you use to give you such results? ]]]]]
>
>The resulting PLL accumulated jitter,
>phase jitter, or autocorrelation record will not continue to increase
>past a value related to the PLL loops bandwidth, however (assuming the
>loop is stable). =3D20
>
>
>[[[[[Phase jitter is bounded?? What equipment shows that! ]]]]]]
>
>This is due to the intrinsic PLL loop gain. =3D20
>
>[[[[[No, you are wrong, again. Even when the PLL is in the locked
>operation, the feedback can only correct the VCO jitter within the loop
>bandwidth. Beyond that, the feedback cannot do anything, period. When
>the overall PLL output RMS jitter is measured to be bounded across all
>frequencies, then the VCO RMS jitter *must also be bounded across all
>frequencies*. =3D20
>
>On the other hand, phase jitter for a locked PLL is unbounded due to
>probability of random events. ]]]]]
>
>
>My point is that the way to deal with both VCO's and the VCO-PLL
>integrated loop is with autocorrelation analysis. We have addressed a
>lot of data recovery issues, PLL and VCO design issues using these
>methods, solved a lot of problems. Unfortunately, these methods are
>not used that heavily (there is one exception in the industry however),
>but we see value in the approach especially in regard to Chris's
initial
>email where you want to analyze peaking and jitter multiplication from
>TX to RX, including models of the reference PLL or oscillator and
signal
>path.
>
>[[[[[I do not doubt the validity of autocorrelation theories, but I
>highly suspect that you have valid data to support your claims.
>Especially when your environment gives you data in the form of Y =3D3D =
mX
=3D
>+
>b. ]]]]]
>
>
>
>Alfred P. Neves <*)))))><{
>
>=3D20
>Hillsboro Office:
>735 SE 16th Ave.
>Hillsboro, OR, 97123
>(503) 679 2429 Voice
>(503) 210 7727 Fax
>=3D20
>Main Corporate office:
>Teraspeed Consulting Group LLC=3D20
>121 North River Drive=3D20
>Narragansett, RI 02882
>(401) 284-1827 Business
>(401) 284-1840 Fax=3D20
>http://www.teraspeed.com
>=3D20
>Teraspeed is the registered service mark=3D20
>of Teraspeed Consulting Group LLC
>=3D20
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of steve weir
>Sent: Wednesday, March 21, 2007 8:29 PM
>To: Tang, George; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Jitter transfer vs. accumulation
>
>
>George, thanks for the reply.
>At 05:02 PM 3/21/2007, you wrote:
> =20
>
>>Steve,
>>
>>Please see comments in {{{{{ }}}}} below.
>>
>>
>>George
>>
>>
>>snip
>>-----Original Message-----
>>From: steve weir [mailto:weirsi@xxxxxxxxxx]=3D3D20
>>Sent: Tuesday, March 20, 2007 4:10 AM
>>To: Tang, George; Alfred P. Neves; Chris Cheng; si-list@xxxxxxxxxxxxx
>>Subject: Re: [SI-LIST] Re: Jitter transfer vs. accumulation
>>
>>George, please correct me if I am wrong, but I believe:
>>
>>1) That the inverter gain K is both temperature and supply =
voltage=3D20
>>dependent.
>>
>>{{{{{True, not a function of time. }}}}}
>>
>> =20
>>
>Good. Then do we also agree that when the supply voltage and=3D20
>temperature both vary with time that the gain does as well? If not
why?
>
>
> =20
>
>>2) That even in an isothermal, constant supply, and zero noise =3D
>> =20
>>
>Vref=3D3D20=3D20
> =20
>
>>environment, running open-loop that in the limit any single
VCO=3D3D20=3D20
>>output interval can vary from epsilon*ring_stages to
approximately=3D3D20 =3D
>> =20
>>
>
> =20
>
>>Vcc/Vths_nom*UI*ring_stages.
>>
>>{{{{{You CANNOT rewrite the laws of physics with your funny
formula.=3D20
>>The input sensitivity (in mV) is not proportional to VCC voltage
nor=3D20
>>inversely proportional to Vth. Throwing such formulae around does
not=3D20
>>fool people into believing you. }}}}}
>> =20
>>
>
>George there is no attempt to "fool people". Please keep the=3D20
>discussion on a professional level.
>
>The minimum period for one inverter in the presence of a large
enough=3D20
>shot noise pulse is the inverter minimum delay time epsilon, is it not?
>An arbitrarily large noise shot pulse can only defer a transition =
by=3D20
>a maximum amount of time. If you object to the approximation of=3D20
>Vcc/Vths I am open to discussion of alternative approximations.
>
>
> =20
>
>>Maybe I don't understand what you mean by
>>
>>"My assertion is that when temperature,
>>voltage, low noise level and fixed noise frequency parameters are
all=3D20
>>in steady-state condition, the open-loop VCO output jitter shall =
be=3D20
>>constant."
>>
>>{{{{{The output RMS jitter shall be constant. When we talk about
PLL=3D20
>>or VCO jitter, we usually talk about the RMS jitter. Phase jitter
is=3D20
>>meaningless unless you specify the sample size. }}}}}
>>
>>
>>That sounds like Dj induced from power supply feedback.
>>
>>
>>{{{{{Whatever the cause, the result is the same. }}}}}
>> =20
>>
>
>OK I think we agree there is a big difference between peak jitter
and=3D20
>RMS jitter. So, I think we can put that aside and concentrate on RMS
>jitter.
>
>
> =20
>
>>My interpretation is that even in this pristine environment of
a=3D3D20=3D20
>>perfect power supply the oscillator exhibits unbounded Rj. If it =3D
>> =20
>>
>is=3D3D20
>
> =20
>
>>bounded, what limits it?
>>
>>{{{{{Alfred made the initial postulate that open-loop VCO has rms=3D20
>>jitter governed by his funny equation Y=3D3DmX + b, where Y is the
rms=3D20
>>jitter, X is the time duration of measurement, and m > 0. This
shows=3D20
>>that as time goes to infinity, the rms jitter of the open-loop VCO
also
>> =20
>>
>
> =20
>
>>goes to infinity. He further claimed that with the feedback loop
of=3D20
>>the PLL, the rms jitter became bounded. You don't think Alfred =
was=3D20
>>crazy enough to make the mistake of comparing phase jitter of VCO
to=3D20
>>the RMS jitter of the PLL, do you? That will be comparing apples
to=3D20
>>bananas, let alone oranges.
>>
>>My claim is that both VCO rms jitter and PLL rms jitter are
bounded,=3D20
>>and the closed-loop feedback circuit simply attenuates the
open-loop=3D20
>>rms jitter. Both circuits have unbounded phase jitters. }}}}}
>> =20
>>
>
>So it sounds to me that we agree that Rj is unbounded. My
experience=3D20
>agrees with Al's assertion that due to Rj, RMS jitter does creep=3D20
>upwards with time. This is the evil of the 1/f noise corner=3D20
>exhibited by every DC amplifier I have encountered. If noise
density=3D20
>/ square root frequency were the RMS value wouldn't creep. What is
>wrong here?
>
>I have to agree with you that an indefinite divided by a definite =
is=3D20
>still indefinite. Al will have to address whether he was saying
that=3D20
>feedback bounds peak jitter, and if so why.
>
>
>
> =20
>
>>In my world, ( which may be perverse ) the only way that we get
to=3D3D20 =3D
>> =20
>>
>
> =20
>
>>bound Rj is to bound the number of UIs, and we don't get to do =3D
>> =20
>>
>that=3D3D20=3D20
> =20
>
>>until we close the feedback loop.
>>
>>
>>{{{{{Sorry, another funny theory of yours. RJ is a statistical=3D20
>>probability. Bounding the number of UIs does not bound the=3D20
>>peak-to-peak RJ. Closing the feedback loop does not bound RJ p-p. =
=3D20
>>}}}}}
>>
>> =20
>>
>
>I acknowledged that I mispoke on this in my private e-mail to=3D20
>you. The likelihood that an event outside some magnitude will =
occur=3D20
>shrinks with reduced exposure. Applying feedback cannot reduce =
the=3D20
>limit which remains indefinite. It does however effectively reduce
>sigma.
>
> =20
>
>>In my mind this goes back to=3D3D20
>>Chris' issue which is that from the loop cut-off up to 1/UI the =3D
>> =20
>>
>VCO=3D3D20=3D20
> =20
>
>>accumulates phase error based on thermal, power supply noise,
and=3D3D20=3D20
>>reference voltage noise disturbances with little or no=3D3D20 =3D
>> =20
>>
>attenuation.
>
> =20
>
>>It is only well within the closed loop B/W that=3D3D20 feedback =3D
>> =20
>>
>diminishes=3D20
> =20
>
>>those error terms WRT the apparent reference=3D3D20 timing source. Is =
=3D
>> =20
>>
>this
>
> =20
>
>>incorrect?
>>
>>
>>{{{{{No. Phase jitter is always accumulated regardless open-loop
or=3D20
>>closed-loop. Closing the loop does attenuate the phase error
within=3D20
>>the bandwidth, but RMS RJ does not go to zero. }}}}}
>>
>> =20
>>
>
>We agree that feedback cannot drive jitter to zero. I remain at
odds=3D20
>with your blanket assertion that phase jitter accumulates in a
closed=3D20
>loop as well as an open loop. Jitter is a noise term, and all my=3D20
>references state that a feedback loop works to reduce noise terms =
of=3D20
>the elements within the loop. Do you have a reference as to why
this=3D20
>would not be so in this situation?
>
>It appears we agree that the loop acts to reduce phase error which
is=3D20
>what we care about and where Chris' complaint came from. We =
appear=3D20
>to also agree that as we slide down the GBW curve the amount of=3D20
>correction shrinks. Do we agree that well above the 0db crossing
the=3D20
>loop does almost nothing to adjust the VCO phase to match the=3D20
>incoming data stream? If we agree then I think Chris' point is=3D20
>made. If we don't, I would like to know why. It may be for the=3D20
>particular standards that Chris is unhappy about that other =
concerns=3D20
>drove the cut-off frequencies selected. But from the narrow=3D20
>perspective of the PLL bandwidth impact on CDR function I see his
point.
>
> =20
>
>>If so, why? Absent feedback, I=3D3D20
>>expect the each inverter in the oscillator to exhibit 1/f noise =3D
>> =20
>>
>like=3D3D20
>
> =20
>
>>any other amplifier no matter how clean the power supply is. Do =3D
>> =20
>>
>you=3D3D20
>
> =20
>
>>agree? If not, why?
>>
>>{{{{{Sure. But with feedback, the same is still true that the
random=3D20
>>noise is still present. That is not the point of the argument. }}}}}
>>
>> =20
>>
>
>I am not sure if we agree that feedback attenuates all types of noise.
>Do we?
>
>
> =20
>
>>I agree that designing a stable VCO and feeding it with clean
low=3D3D20=3D20
>>impedance power are important towards achieving low jitter. But =
I=3D20
>>am=3D3D20 having difficulty following the apparent idea that
achieving=3D20
>>those=3D3D20 goals eliminates jitter components as opposed to reducing =
=3D
>> =20
>>
>them
>
> =20
>
>>to=3D3D20 small values. Is there a conflict between semantics of
"very=3D20
>>small"=3D3D20 and "zero"?
>>
>>
>>{{{{{I never said that jitter can be eliminated. I only said that
RMS=3D20
>>jitter is bounded for both VCO and PLL. Alfred made the assertion
that
>> =20
>>
>
> =20
>
>>VCO has unbounded rms jitter, but PLL has bounded rms jitter. =
The=3D20
>>funny equations you guys put out do not help with your arguments =
at=3D20
>>all. }}}}}
>>
>> =20
>>
>
>Al is very capable and knowledgeable in this area. I do not speak=3D20
>for him. It would be a lot easier to reach a common understanding
if=3D20
>you could tone down the open hostility.
>
>
> =20
>
>>Regards,
>>
>>
>>Steve.
>> =20
>>
>snip=3D20
>
> =20
>
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