[SI-LIST] Re: Jitter transfer vs. accumulation
- From: "Tang, George" <George.Tang@xxxxxxx>
- To: "steve weir" <weirsi@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 22 Mar 2007 21:14:30 -0600
Steve,=20
Please see comments below in [[[[[ ]]]]].=20
George=20
=20
Note: Effective October 14, 2006, My LSI Logic Email address will change
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-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]=20
Sent: Wednesday, March 21, 2007 8:29 PM
To: Tang, George; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Jitter transfer vs. accumulation
George, thanks for the reply.
At 05:02 PM 3/21/2007, you wrote:
>Steve,
>
>Please see comments in {{{{{ }}}}} below.
>
>
>George
>
>
>snip
>-----Original Message-----
>From: steve weir [mailto:weirsi@xxxxxxxxxx]=3D20
>Sent: Tuesday, March 20, 2007 4:10 AM
>To: Tang, George; Alfred P. Neves; Chris Cheng; si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Re: Jitter transfer vs. accumulation
>
>George, please correct me if I am wrong, but I believe:
>
>1) That the inverter gain K is both temperature and supply voltage
>dependent.
>
>{{{{{True, not a function of time. }}}}}
>
Good. Then do we also agree that when the supply voltage and=20
temperature both vary with time that the gain does as well? If not why?
[[[[[Yes. But I have already made the pre-qualification that power
noise is low and temperature is in steady state equilibrium, given that
precision power source is not hard to find. ]]]]]
>2) That even in an isothermal, constant supply, and zero noise =
Vref=3D20
>environment, running open-loop that in the limit any single VCO=3D20
>output interval can vary from epsilon*ring_stages to approximately=3D20
>Vcc/Vths_nom*UI*ring_stages.
>
>{{{{{You CANNOT rewrite the laws of physics with your funny formula.
>The input sensitivity (in mV) is not proportional to VCC voltage nor
>inversely proportional to Vth. Throwing such formulae around does not
>fool people into believing you. }}}}}
George there is no attempt to "fool people". Please keep the=20
discussion on a professional level.
The minimum period for one inverter in the presence of a large enough=20
shot noise pulse is the inverter minimum delay time epsilon, is it not?=20
[[[[[Absolutely NOT. ]]]]]=20
An arbitrarily large noise shot pulse can only defer a transition by=20
a maximum amount of time. If you object to the approximation of=20
Vcc/Vths I am open to discussion of alternative approximations.
[[[[[It is analyzed in terms of signal-to-noise ratio. You forgot that
there is a signal. ]]]]]
>Maybe I don't understand what you mean by
>
>"My assertion is that when temperature,
>voltage, low noise level and fixed noise frequency parameters are all
in
>steady-state condition, the open-loop VCO output jitter shall be
>constant."
>
>{{{{{The output RMS jitter shall be constant. When we talk about PLL
or
>VCO jitter, we usually talk about the RMS jitter. Phase jitter is
>meaningless unless you specify the sample size. }}}}}
>
>
>That sounds like Dj induced from power supply feedback.
>
>
>{{{{{Whatever the cause, the result is the same. }}}}}
OK I think we agree there is a big difference between peak jitter and=20
RMS jitter. So, I think we can put that aside and concentrate on RMS
jitter.
[[[[[Fine. ]]]]]
>My interpretation is that even in this pristine environment of a=3D20
>perfect power supply the oscillator exhibits unbounded Rj. If it =
is=3D20
>bounded, what limits it?
>
>{{{{{Alfred made the initial postulate that open-loop VCO has rms
jitter
>governed by his funny equation Y=3DmX + b, where Y is the rms jitter, X
is
>the time duration of measurement, and m > 0. This shows that as time
>goes to infinity, the rms jitter of the open-loop VCO also goes to
>infinity. He further claimed that with the feedback loop of the PLL,
>the rms jitter became bounded. You don't think Alfred was crazy enough
>to make the mistake of comparing phase jitter of VCO to the RMS jitter
>of the PLL, do you? That will be comparing apples to bananas, let
alone
>oranges.
>
>My claim is that both VCO rms jitter and PLL rms jitter are bounded,
and
>the closed-loop feedback circuit simply attenuates the open-loop rms
>jitter. Both circuits have unbounded phase jitters. }}}}}
So it sounds to me that we agree that Rj is unbounded. =20
[[[[[How many times do I have to repeat my assertion that both VCO rms
jitter and PLL rms jitter are bounded! ]]]]]=20
My experience=20
agrees with Al's assertion that due to Rj, RMS jitter does creep=20
upwards with time. This is the evil of the 1/f noise corner=20
exhibited by every DC amplifier I have encountered. If noise density=20
/ square root frequency were the RMS value wouldn't creep. What is
wrong here?
[[[[[Wrong! I repeat that rms jitter is bounded! Just think about what
you are saying. If RMS jitter is unbounded, we would never be able to
close timing and make a circuit work for more than a few days or a few
weeks. There are products out on the market that run at 10GHz and
beyond. The timing margin in these circuits is probably only tens of
ps. How can they run for months or years without data errors? In fact,
you wouldn't even be able to make any measurements if RMS jitter is
unbounded. If you leave your oscilloscope running for days, the
measurements you take on day one will be different from that of day two
or day three because the scope RMS jitter noise will grow each day along
with your DUT RMS jitter noise. In that case, you are out of a job
because you cannot make repeatable measurements. ]]]]] =20
I have to agree with you that an indefinite divided by a definite is=20
still indefinite. Al will have to address whether he was saying that=20
feedback bounds peak jitter, and if so why.
>In my world, ( which may be perverse ) the only way that we get to=3D20
>bound Rj is to bound the number of UIs, and we don't get to do =
that=3D20
>until we close the feedback loop.
>
>
>{{{{{Sorry, another funny theory of yours. RJ is a statistical
>probability. Bounding the number of UIs does not bound the
peak-to-peak
>RJ. Closing the feedback loop does not bound RJ p-p. }}}}}
>
I acknowledged that I mispoke on this in my private e-mail to=20
you. The likelihood that an event outside some magnitude will occur=20
shrinks with reduced exposure. Applying feedback cannot reduce the=20
limit which remains indefinite. It does however effectively reduce
sigma.
>In my mind this goes back to=3D20
>Chris' issue which is that from the loop cut-off up to 1/UI the =
VCO=3D20
>accumulates phase error based on thermal, power supply noise, and=3D20
>reference voltage noise disturbances with little or no=3D20
>attenuation. It is only well within the closed loop B/W that=3D20
>feedback diminishes those error terms WRT the apparent reference=3D20
>timing source. Is this incorrect?
>
>
>{{{{{No. Phase jitter is always accumulated regardless open-loop or
>closed-loop. Closing the loop does attenuate the phase error within
the
>bandwidth, but RMS RJ does not go to zero. }}}}}
>
We agree that feedback cannot drive jitter to zero. I remain at odds=20
with your blanket assertion that phase jitter accumulates in a closed=20
loop as well as an open loop. Jitter is a noise term, and all my=20
references state that a feedback loop works to reduce noise terms of=20
the elements within the loop. Do you have a reference as to why this=20
would not be so in this situation?
[[[[[Study statistics and probability theory, and maybe quantum
theory.]]]]]=20
It appears we agree that the loop acts to reduce phase error which is=20
what we care about and where Chris' complaint came from. We appear=20
to also agree that as we slide down the GBW curve the amount of=20
correction shrinks. Do we agree that well above the 0db crossing the=20
loop does almost nothing to adjust the VCO phase to match the=20
incoming data stream? If we agree then I think Chris' point is=20
made. If we don't, I would like to know why. It may be for the=20
particular standards that Chris is unhappy about that other concerns=20
drove the cut-off frequencies selected. But from the narrow=20
perspective of the PLL bandwidth impact on CDR function I see his point.
[[[[[You are right about the GBW curve. But as long as the curve is
above 0 dB, the feedback loop is still making correction, but the
remaining error grows. Chris' comment about the standards' selection is
a whole other story because the standards must cover all types of
environments and conditions that the chip may be subjected to. I will
not go into that here. ]]]]]]=20
>If so, why? Absent feedback, I=3D20
>expect the each inverter in the oscillator to exhibit 1/f noise =
like=3D20
>any other amplifier no matter how clean the power supply is. Do =
you=3D20
>agree? If not, why?
>
>{{{{{Sure. But with feedback, the same is still true that the random
>noise is still present. That is not the point of the argument. }}}}}
>
I am not sure if we agree that feedback attenuates all types of noise.
Do we?
[[[[[No, feedback does not attenuate all types of noise. ]]]]]
>I agree that designing a stable VCO and feeding it with clean low=3D20
>impedance power are important towards achieving low jitter. But I
am=3D20
>having difficulty following the apparent idea that achieving those=3D20
>goals eliminates jitter components as opposed to reducing them to=3D20
>small values. Is there a conflict between semantics of "very =
small"=3D20
>and "zero"?
>
>
>{{{{{I never said that jitter can be eliminated. I only said that RMS
>jitter is bounded for both VCO and PLL. Alfred made the assertion that
>VCO has unbounded rms jitter, but PLL has bounded rms jitter. The
funny
>equations you guys put out do not help with your arguments at all.
>}}}}}
>
Al is very capable and knowledgeable in this area. I do not speak=20
for him. It would be a lot easier to reach a common understanding if=20
you could tone down the open hostility.
[[[[[If you would stop throwing out false equations. ]]]]]=20
>Regards,
>
>
>Steve.
snip=20
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