Posts for si-list, 03-2007

Browse: Last Month: 02-2007 Main Archive Page Next Month: 04-2007

» [SI-LIST] Re: Coplanar wave structure on PCB -
» [SI-LIST] DDR2 input slew rate measurement -
» [SI-LIST] DDR2 input slew rate measurement -
» [SI-LIST] Future Directions in IC and Package Design Workshop (FDIP) -
» [SI-LIST] IBIS model for 2mm connector -
» [SI-LIST] Re: DDR2 inteface consultant needed -
» [SI-LIST] Re: DDR2 inteface consultant needed -
» [SI-LIST] Re: DDR2 inteface consultant needed -
» [SI-LIST] Re: DDR2 inteface consultant needed -
» [SI-LIST] Re: DDR2 inteface consultant needed -
» [SI-LIST] Re: DDR2 inteface consultant needed -
» [SI-LIST] Re: PCI-E Length Matching -
» [SI-LIST] Re: USB 2.0 cable and connector model -
» [SI-LIST] PCI-E Length Matching -
» [SI-LIST] Re: DDR2 inteface consultant needed -
» [SI-LIST] Join the Anatrim revolution -
» [SI-LIST] DDR2 inteface consultant needed -
» [SI-LIST] USB 2.0 cable and connector model -
» [SI-LIST] ASIC characterization -
» [SI-LIST] Noise in ICs -
» [SI-LIST] Re: Bounded vs Unbounded jitter (was : Jitter transfer vs. accumulation) -
» [SI-LIST] Macromodeling tools @ Politecnico di Torino, EMC group - Update -
» [SI-LIST] Re: DDR timing equation question -
» [SI-LIST] Re: Reference ground plane below ethernet differential pairs - good or bad? -
» [SI-LIST] DDR timing equation question -
» [SI-LIST] Re: Reference ground plane below ethernet differential pairs - good or bad? -
» [SI-LIST] Re: Bounded vs Unbounded jitter (was : Jitter transfer vs. accumulation) -
» [SI-LIST] European IBIS Summit @ DATe 2007 - Thrid Call for Participation -
» [SI-LIST] Re: Reference ground plane below ethernet differential pairs - good or bad? -
» [SI-LIST] noise analysis -
» [SI-LIST] Reference ground plane below ethernet differential pairs - good or bad? -
» [SI-LIST] Re: timing analysis -
» [SI-LIST] Re: timing analysis -
» [SI-LIST] Creating local power planes -
» [SI-LIST] Re: Insertion and Return Loss -
» [SI-LIST] Wolfgang Maichen/USW/Teradyne is out of the office. -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Why 4-way cross in schematic to be avoided -
» [SI-LIST] Re: Bounded vs Unbounded jitter (was : Jitter transfer vs. accumulation) -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Bounded vs Unbounded jitter (was : Jitter transfer vs. accumulation) -
» [SI-LIST] Bounded vs Unbounded jitter (was : Jitter transfer vs. accumulation) -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Why 4-way cross in schematic to be avoided -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: timing analysis -
» [SI-LIST] Re: Using Load Switching FETs -
» [SI-LIST] timing analysis -
» [SI-LIST] Re: Insertion and Return Loss -
» [SI-LIST] Why 4-way cross in schematic to be avoided -
» [SI-LIST] Re: Using Load Switching FETs -
» [SI-LIST] Using Load Switching FETs -
» [SI-LIST] Insertion and Return Loss -
» [SI-LIST] FREE SEMINAR: Tuesday 3/27/07 Noon-2PM (Santa Clara) -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Google: Hiring SI Engineers, Mountain View, CA -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Al Neves of Teraspeed Consulting and Eric Bogatin at the Agilent Roadshow -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Regarding Loop simulator. -
» [SI-LIST] Regarding Loop simulator. -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Free Seminar on Buried Capacitance applications during PCB West -
» [SI-LIST] Re: Good book about jitter.... -
» [SI-LIST] Re: impedance and Characteristic impedance -
» [SI-LIST] Clocking Architecture and Oscillator jitter.... -
» [SI-LIST] Re: Good book about jitter.... -
» [SI-LIST] Re: Good book about jitter.... -
» [SI-LIST] Re: Good book about jitter.... -
» [SI-LIST] Re: Good book about jitter.... -
» [SI-LIST] Good book about jitter.... -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Fwd: Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: impedance and Characteristic impedance -
» [SI-LIST] Re: impedance and Characteristic impedance -
» [SI-LIST] Re: impedance and Characteristic impedance -
» [SI-LIST] SI job opening in Intel - Bangalore, India -
» [SI-LIST] impedance and Characteristic impedance -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] High Speed PCB and System Design Course in Austin, Texas -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Source synchronous interface delay measurement -
» [SI-LIST] Re: Source synchronous interface delay measurement -
» [SI-LIST] Re: Source synchronous interface delay measurement -
» [SI-LIST] Suggested References for Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: unsubscribe now! please -
» [SI-LIST] Re: R: How to Route XFP 10G electrical trace? -
» [SI-LIST] Re: R: How to Route XFP 10G electrical trace? -
» [SI-LIST] Re: R: How to Route XFP 10G electrical trace? -
» [SI-LIST] Re: R: How to Route XFP 10G electrical trace? -
» [SI-LIST] Re: R: How to Route XFP 10G electrical trace? -
» [SI-LIST] Re: R: How to Route XFP 10G electrical trace? -
» [SI-LIST] Re: DecapPlacement -
» [SI-LIST] Re: DecapPlacement -
» [SI-LIST] Re: R: How to Route XFP 10G electrical trace? -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Re: DecapPlacement -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: DecapPlacement -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Re: DecapPlacement -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: DecapPlacement -
» [SI-LIST] AMD Characterization Engineer -
» [SI-LIST] Re: OLL coupon BTS115 -
» [SI-LIST] OLL coupon for "What is Characteristic Impedance" -
» [SI-LIST] Re: DecapPlacement -
» [SI-LIST] Source synchronous interface delay measurement -
» [SI-LIST] Re: DecapPlacement -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: DecapPlacement -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] republican microscopy -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Hello, Assistance Required -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Diff Tight vs Loosely coupled -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Re: Diff Tight vs Loosely coupled -
» [SI-LIST] Diff Tight vs Loosely coupled -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Jitter transfer vs. accumulation -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Jitter transfer vs. accumulation -
» [SI-LIST] Re: How to Route XFP 10G electrical trace? -
» [SI-LIST] Re: DecapPlacement -
» [SI-LIST] DecapPlacement -
» [SI-LIST] Express of Infiniband in the backplane -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] European IBIS Summit @ DATe 2007 - Second Call for Participation -
» [SI-LIST] Re: SI Symposium -
» [SI-LIST] SI Symposium -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Re: How to Route XFP 10G electrical trace? -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Re: R: How to Route XFP 10G electrical trace? -
» [SI-LIST] Re: How to Route XFP 10G electrical trace? -
» [SI-LIST] Re: How to Route XFP 10G electrical trace? -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Re: Propagation delay difference -
» [SI-LIST] Propagation delay difference -
» [SI-LIST] R: How to Route XFP 10G electrical trace? -
» [SI-LIST] MII to AUI interface PHY transceiver -
» [SI-LIST] Re: How to get RLC matrix from spice model -
» [SI-LIST] Re: Use of Li-ion batteries -
» [SI-LIST] Re: Use of Li-ion batteries -
» [SI-LIST] How to Route XFP 10G electrical trace? -
» [SI-LIST] test -
» [SI-LIST] Re: Question on 60Hz magnetic field strengths -
» [SI-LIST] Re: Use of Li-ion batteries -
» [SI-LIST] Use of Li-ion batteries -
» [SI-LIST] SI/PI enginner position at Altera Pacakge Group -
» [SI-LIST] IBIS Seminar -
» [SI-LIST] Question on 60Hz magnetic field strengths -
» [SI-LIST] DesignCon 2007 podcast -
» [SI-LIST] Re: Buried capacitance and vias -
» [SI-LIST] Google Power Engineer: EE board level dc-dc converters (Mtn View, CA) -
» [SI-LIST] Buried capacitance and vias -
» [SI-LIST] Oscillation killer -
» [SI-LIST] Isolating pwb and chassis grounds -
» [SI-LIST] Re: Oscillation killer -
» [SI-LIST] MPX bus impedance -
» [SI-LIST] Re: How to get RLC matrix from spice model -
» [SI-LIST] Re: Oscillation killer -
» [SI-LIST] Oscillation killer -
» [SI-LIST] Consulting -
» [SI-LIST] Re: PCB Trace impedance algorithms - Free trace calculator -
» [SI-LIST] Re: Termination Topology for Bidirectional Bus -
» [SI-LIST] Re: PCB Trace impedance algorithms - Free trace calculator -
» [SI-LIST] Re: Termination Topology for Bidirectional Bus -
» [SI-LIST] Re: interconnection technology -
» [SI-LIST] Re: Testing method of differential intra-pair skew -
» [SI-LIST] Re: Termination Topology for Bidirectional Bus -
» [SI-LIST] Re: interconnection technology -
» [SI-LIST] Re: Termination Topology for Bidirectional Bus -
» [SI-LIST] Re: Termination Topology for Bidirectional Bus -
» [SI-LIST] interconnection technology -
» [SI-LIST] Termination Topology for Bidirectional Bus -
» [SI-LIST] how to measure differential intra-pair skew -
» [SI-LIST] Re: How to get RLC matrix from spice model -
» [SI-LIST] Re: Testing method of differential intra-pair skew -
» [SI-LIST] Re: How to get RLC matrix from spice model -
» [SI-LIST] Re: Testing method of differential intra-pair skew -
» [SI-LIST] Testing method of differential intra-pair skew -
» [SI-LIST] Re: How to get RLC matrix from spice model -
» [SI-LIST] Re: SI Tool Suggestion -
» [SI-LIST] Re: How to get RLC matrix from spice model -
» [SI-LIST] Via filler -
» [SI-LIST] How to get RLC matrix from spice model -