[SI-LIST] Re: Jitter transfer vs. accumulation

George,


>{{{{{Alfred made the initial postulate that open-loop VCO has rms 
>jitter governed by his funny equation Y=mX + b, where Y is the rms 
>jitter, X is the time duration of measurement, and m > 0.  This shows 
>that as time goes to infinity, the rms jitter of the open-loop VCO also

>goes to infinity.

No George, this is not what I said.  It is the autocorrelation record of
the VCO that increases linearly on a log-log plot, where the axis are
log(RMS jitter) and log(time interval length), where this is not to be
confused with an RMS jitter or whether it is bounded or not.  I already
provided numerous references regarding this and can also provide
numerous measurements for several VCO's to illustrate VCO RMS jitter
characteristics versus measurement interval.  We have used this analysis
100's of times for closed (and open loop) PLL analysis to determine the
PLL loop bandwidth and peaking in the PLL loop response.  You can also
use this analysis to analyze jitter problems like spurious response due
to charge pump leakage, power supply junk like switching noise or HF
digital, XTALK in the substrate, SSO, and jitter multiplication from PLL
to PLL.  The basis for this analysis is work by John McNeil in
collaboration with Analog Devices in the mid 90's - have you read the
reference already provided, I can send you a copy if need be?   I didn't
originate the concept, just use the practical elements to analyze PLL's
and VCO's.  Before you belittle this, become dismissive, or make any
more personally targeted comments it may behoove you to do a bit of
homework.   And once again, you are asked to significantly raise the
level of your professionalism in your communications.   

> He further claimed that with the feedback loop of 
>the PLL, the rms jitter became bounded.  You don't think Alfred was 
>crazy enough to make the mistake of comparing phase jitter of VCO to 
>the RMS jitter of the PLL, do you?  That will be comparing apples to 
>bananas, let alone oranges

No, I did not say this either.  The reference was regarding the
autocorrelation record, NOT any comment regarding characteristics of VCO
RMS jitter.  A VCO has certain properties:   It has poor frequency
stability, it is temperature sensitive, it is not WSS (wide sense
stationary), it has a LOT of low frequency jitter due to numerous 1/f
noise sources, it also has unbounded RMS jitter, but the estimate of the
RMS jitter is difficult to measure since:   Measure the RMS of a VCO
over a certain time T, remeasure the RMS jitter later over the same time
interval and you will arrive at a different RMS number since it is not a
stationary process.   Sample size really has little to do with this.
BTW, do you have data on "stable" VCO's in terms of PPM frequency drift
versus time, after you claim the temperature stabilizes in 1-2 hours.



NOW, place the VCO into a PLL loop that is locked on a stable input
signal, the VCO accumulated phase jitter  is shaped by the PLL loop
response.  The RMS RJ jitter measured (using some RJ-DJ extraction) will
be unbounded  - by definition.    The resulting PLL accumulated jitter,
phase jitter, or autocorrelation record will not continue to increase
past a value related to the PLL loops bandwidth, however (assuming the
loop is stable).   This is due to the intrinsic PLL loop gain.  

My point is that the way to deal with both VCO's and the VCO-PLL
integrated loop is with autocorrelation analysis.  We have addressed a
lot of data recovery issues, PLL and VCO design issues using these
methods, solved a lot of problems.   Unfortunately, these methods are
not used that heavily (there is one exception in the industry however),
but we see value in the approach especially in regard to Chris's initial
email where you want to analyze peaking and jitter multiplication from
TX to RX, including models of the reference PLL or oscillator and signal
path.






Alfred P. Neves      <*)))))><{

 
Hillsboro Office:
735 SE 16th Ave.
Hillsboro, OR, 97123
(503) 679 2429 Voice
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of Teraspeed Consulting Group LLC
 


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: Wednesday, March 21, 2007 8:29 PM
To: Tang, George; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Jitter transfer vs. accumulation


George, thanks for the reply.
At 05:02 PM 3/21/2007, you wrote:
>Steve,
>
>Please see comments in {{{{{ }}}}} below.
>
>
>George
>
>
>snip
>-----Original Message-----
>From: steve weir [mailto:weirsi@xxxxxxxxxx]=20
>Sent: Tuesday, March 20, 2007 4:10 AM
>To: Tang, George; Alfred P. Neves; Chris Cheng; si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Re: Jitter transfer vs. accumulation
>
>George, please correct me if I am wrong, but I believe:
>
>1) That the inverter gain K is both temperature and supply voltage 
>dependent.
>
>{{{{{True, not a function of time. }}}}}
>
Good.  Then do we also agree that when the supply voltage and 
temperature both vary with time that the gain does as well?  If not why?


>2) That even in an isothermal, constant supply, and zero noise Vref=20 
>environment, running open-loop that in the limit any single VCO=20 
>output interval can vary from epsilon*ring_stages to approximately=20 
>Vcc/Vths_nom*UI*ring_stages.
>
>{{{{{You CANNOT rewrite the laws of physics with your funny formula. 
>The input sensitivity (in mV) is not proportional to VCC voltage nor 
>inversely proportional to Vth.  Throwing such formulae around does not 
>fool people into believing you.  }}}}}

George there is no attempt to "fool people".  Please keep the 
discussion on a professional level.

The minimum period for one inverter in the presence of a large enough 
shot noise pulse is the inverter minimum delay time epsilon, is it not?
An arbitrarily large noise shot pulse can only defer a transition by 
a maximum amount of time.  If you object to the approximation of 
Vcc/Vths I am open to discussion of alternative approximations.


>Maybe I don't understand what you mean by
>
>"My assertion is that when temperature,
>voltage, low noise level and fixed noise frequency parameters are all 
>in steady-state condition, the open-loop VCO output jitter shall be 
>constant."
>
>{{{{{The output RMS jitter shall be constant.  When we talk about PLL 
>or VCO jitter, we usually talk about the RMS jitter.  Phase jitter is 
>meaningless unless you specify the sample size.  }}}}}
>
>
>That sounds like Dj induced from power supply feedback.
>
>
>{{{{{Whatever the cause, the result is the same.  }}}}}

OK I think we agree there is a big difference between peak jitter and 
RMS jitter.  So, I think we can put that aside and concentrate on RMS
jitter.


>My interpretation is that even in this pristine environment of a=20 
>perfect power supply the oscillator exhibits unbounded Rj.  If it is=20

>bounded, what limits it?
>
>{{{{{Alfred made the initial postulate that open-loop VCO has rms 
>jitter governed by his funny equation Y=mX + b, where Y is the rms 
>jitter, X is the time duration of measurement, and m > 0.  This shows 
>that as time goes to infinity, the rms jitter of the open-loop VCO also

>goes to infinity.  He further claimed that with the feedback loop of 
>the PLL, the rms jitter became bounded.  You don't think Alfred was 
>crazy enough to make the mistake of comparing phase jitter of VCO to 
>the RMS jitter of the PLL, do you?  That will be comparing apples to 
>bananas, let alone oranges.
>
>My claim is that both VCO rms jitter and PLL rms jitter are bounded, 
>and the closed-loop feedback circuit simply attenuates the open-loop 
>rms jitter.  Both circuits have unbounded phase jitters.  }}}}}

So it sounds to me that we agree that Rj is unbounded.  My experience 
agrees with Al's assertion that due to Rj, RMS jitter does creep 
upwards with time.  This is the evil of the 1/f noise corner 
exhibited by every DC amplifier I have encountered.  If noise density 
/ square root frequency were the RMS value wouldn't creep.  What is
wrong here?

I have to agree with you that an indefinite divided by a definite is 
still indefinite.  Al will have to address whether he was saying that 
feedback bounds peak jitter, and if so why.



>In my world, ( which may be perverse ) the only way that we get to=20 
>bound Rj is to bound the number of UIs, and we don't get to do that=20 
>until we close the feedback loop.
>
>
>{{{{{Sorry, another funny theory of yours.  RJ is a statistical 
>probability.  Bounding the number of UIs does not bound the 
>peak-to-peak RJ.  Closing the feedback loop does not bound RJ p-p.  
>}}}}}
>

I acknowledged that I mispoke on this in my private e-mail to 
you.  The likelihood that an event outside some magnitude will occur 
shrinks with reduced exposure.  Applying feedback cannot reduce the 
limit which remains indefinite.  It does however effectively reduce
sigma.

>In my mind this goes back to=20
>Chris' issue which is that from the loop cut-off up to 1/UI the VCO=20 
>accumulates phase error based on thermal, power supply noise, and=20 
>reference voltage noise disturbances with little or no=20 attenuation.

>It is only well within the closed loop B/W that=20 feedback diminishes 
>those error terms WRT the apparent reference=20 timing source.  Is this

>incorrect?
>
>
>{{{{{No.  Phase jitter is always accumulated regardless open-loop or 
>closed-loop.  Closing the loop does attenuate the phase error within 
>the bandwidth, but RMS RJ does not go to zero.  }}}}}
>

We agree that feedback cannot drive jitter to zero.  I remain at odds 
with your blanket assertion that phase jitter accumulates in a closed 
loop as well as an open loop.  Jitter is a noise term, and all my 
references state that a feedback loop works to reduce noise terms of 
the elements within the loop.  Do you have a reference as to why this 
would not be so in this situation?

It appears we agree that the loop acts to reduce phase error which is 
what we care about and where Chris' complaint came from.  We appear 
to also agree that as we slide down the GBW curve the amount of 
correction shrinks.  Do we agree that well above the 0db crossing the 
loop does almost nothing to adjust the VCO phase to match the 
incoming data stream?  If we agree then I think Chris' point is 
made.  If we don't, I would like to know why.  It may be for the 
particular standards that Chris is unhappy about that other concerns 
drove the cut-off frequencies selected.  But from the narrow 
perspective of the PLL bandwidth impact on CDR function I see his point.

>If so, why?  Absent feedback, I=20
>expect the each inverter in the oscillator to exhibit 1/f noise like=20

>any other amplifier no matter how clean the power supply is.  Do you=20

>agree?  If not, why?
>
>{{{{{Sure.  But with feedback, the same is still true that the random 
>noise is still present.  That is not the point of the argument.  }}}}}
>

I am not sure if we agree that feedback attenuates all types of noise.
Do we?


>I agree that designing a stable VCO and feeding it with clean low=20 
>impedance power are important towards achieving low jitter.  But I 
>am=20 having difficulty following the apparent idea that achieving 
>those=20 goals eliminates jitter components as opposed to reducing them

>to=20 small values.  Is there a conflict between semantics of "very 
>small"=20 and "zero"?
>
>
>{{{{{I never said that jitter can be eliminated.  I only said that RMS 
>jitter is bounded for both VCO and PLL.  Alfred made the assertion that

>VCO has unbounded rms jitter, but PLL has bounded rms jitter.  The 
>funny equations you guys put out do not help with your arguments at 
>all. }}}}}
>

Al is very capable and knowledgeable in this area.  I do not speak 
for him.  It would be a lot easier to reach a common understanding if 
you could tone down the open hostility.


>Regards,
>
>
>Steve.
snip 

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