[SI-LIST] Re: Jitter transfer vs. accumulation

Steve,=20

Please see comments in {{{{{ }}}}} below. =20

=20
George=20
=20

Note: Effective October 14, 2006, My LSI Logic Email address will change
to: george.tang@xxxxxxx

Please update address books and email lists accordingly.


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Tang, George
Sent: Tuesday, March 20, 2007 11:53 AM
To: Scott McMorrow
Cc: steve weir; Alfred P. Neves; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Jitter transfer vs. accumulation

Hello Scott,=3D20

I don't mean to ignore your comments, but your consultants keep coming
up with their theory du jour to fool the people on this list.  Do you
want to do something about this or do you want me to reply to this? =
=3D20

Thanks,=3D20
=3D20
George=3D20
=3D20

Note: Effective October 14, 2006, My LSI Logic Email address will change
to: george.tang@xxxxxxx

Please update address books and email lists accordingly.


-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]=3D20
Sent: Tuesday, March 20, 2007 4:10 AM
To: Tang, George; Alfred P. Neves; Chris Cheng; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Jitter transfer vs. accumulation

George, please correct me if I am wrong, but I believe:

1) That the inverter gain K is both temperature and supply voltage
dependent.

{{{{{True, not a function of time. }}}}}



2) That even in an isothermal, constant supply, and zero noise Vref=3D20
environment, running open-loop that in the limit any single VCO=3D20
output interval can vary from epsilon*ring_stages to approximately=3D20
Vcc/Vths_nom*UI*ring_stages. =20

{{{{{You CANNOT rewrite the laws of physics with your funny formula.
The input sensitivity (in mV) is not proportional to VCC voltage nor
inversely proportional to Vth.  Throwing such formulae around does not
fool people into believing you.  }}}}}=20


Maybe I don't understand what you mean by

"My assertion is that when temperature,
voltage, low noise level and fixed noise frequency parameters are all in
steady-state condition, the open-loop VCO output jitter shall be
constant."

{{{{{The output RMS jitter shall be constant.  When we talk about PLL or
VCO jitter, we usually talk about the RMS jitter.  Phase jitter is
meaningless unless you specify the sample size.  }}}}}=20


That sounds like Dj induced from power supply feedback.


{{{{{Whatever the cause, the result is the same.  }}}}}=20


My interpretation is that even in this pristine environment of a=3D20
perfect power supply the oscillator exhibits unbounded Rj.  If it =
is=3D20
bounded, what limits it?

{{{{{Alfred made the initial postulate that open-loop VCO has rms jitter
governed by his funny equation Y=3DmX + b, where Y is the rms jitter, X =
is
the time duration of measurement, and m > 0.  This shows that as time
goes to infinity, the rms jitter of the open-loop VCO also goes to
infinity.  He further claimed that with the feedback loop of the PLL,
the rms jitter became bounded.  You don't think Alfred was crazy enough
to make the mistake of comparing phase jitter of VCO to the RMS jitter
of the PLL, do you?  That will be comparing apples to bananas, let alone
oranges. =20

My claim is that both VCO rms jitter and PLL rms jitter are bounded, and
the closed-loop feedback circuit simply attenuates the open-loop rms
jitter.  Both circuits have unbounded phase jitters.  }}}}}



In my world, ( which may be perverse ) the only way that we get to=3D20
bound Rj is to bound the number of UIs, and we don't get to do that=3D20
until we close the feedback loop. =20


{{{{{Sorry, another funny theory of yours.  RJ is a statistical
probability.  Bounding the number of UIs does not bound the peak-to-peak
RJ.  Closing the feedback loop does not bound RJ p-p.  }}}}}


In my mind this goes back to=3D20
Chris' issue which is that from the loop cut-off up to 1/UI the VCO=3D20
accumulates phase error based on thermal, power supply noise, and=3D20
reference voltage noise disturbances with little or no=3D20
attenuation.  It is only well within the closed loop B/W that=3D20
feedback diminishes those error terms WRT the apparent reference=3D20
timing source.  Is this incorrect? =20


{{{{{No.  Phase jitter is always accumulated regardless open-loop or
closed-loop.  Closing the loop does attenuate the phase error within the
bandwidth, but RMS RJ does not go to zero.  }}}}}


If so, why?  Absent feedback, I=3D20
expect the each inverter in the oscillator to exhibit 1/f noise =
like=3D20
any other amplifier no matter how clean the power supply is.  Do =
you=3D20
agree?  If not, why?

{{{{{Sure.  But with feedback, the same is still true that the random
noise is still present.  That is not the point of the argument.  }}}}}



I agree that designing a stable VCO and feeding it with clean low=3D20
impedance power are important towards achieving low jitter.  But I =
am=3D20
having difficulty following the apparent idea that achieving those=3D20
goals eliminates jitter components as opposed to reducing them to=3D20
small values.  Is there a conflict between semantics of "very =
small"=3D20
and "zero"?


{{{{{I never said that jitter can be eliminated.  I only said that RMS
jitter is bounded for both VCO and PLL.  Alfred made the assertion that
VCO has unbounded rms jitter, but PLL has bounded rms jitter.  The funny
equations you guys put out do not help with your arguments at all.
}}}}}



Regards,


Steve.



At 07:00 PM 3/19/2007, Tang, George wrote:
>Alfred,=3D3D20
>
>Please see comments below in {{{{[comment]}}}}. =3D3D20
>
>=3D3D20
>George=3D3D20
>=3D3D20
>
>Note: Effective October 14, 2006, My LSI Logic Email address will
change
>to: george.tang@xxxxxxx
>
>Please update address books and email lists accordingly.
>
>
>-----Original Message-----
>From: Alfred P. Neves [mailto:al.neves@xxxxxxxxxxx]=3D3D20
>Sent: Monday, March 19, 2007 3:41 PM
>To: Tang, George; 'Chris Cheng'; si-list@xxxxxxxxxxxxx
>Subject: RE: [SI-LIST] Re: Jitter transfer vs. accumulation
>
>George,
>  =3D3D20
>
>I disagree with you assertion that a free-running VCO, without running
>in a closed-loop PLL environment, has jitter statistics which are not
>invariant WRT time, are therefore non-stationary.  My thinking has been
>that an open loop free running VCO is not stable, and has
non-stationary
>jitter statistics.
>
>{{{{[You are confused, again.  My assertion is that when temperature,
>voltage, low noise level and fixed noise frequency parameters are all
in
>steady-state condition, the open-loop VCO output jitter shall be
>constant.  You have falsely worded my assertion. ]}}}}
>
>
>My understanding is that noise components in the ring oscillator will
>impact the K or voltage sensitivity of the VCO. =3D3D20
>
>{{{{[The gain and the voltage sensitivity of the VCO is determined by
>the inverters in the VCO.  The gain is not a function of the
noise.]}}}}
>
>
>
>For example, input
>referred voltage noise at the at VCO input will modulate the VCO
>frequency which will directly relate to jitter, and this input referred
>noise has 1/f components that create very high low frequency jitter.
>
>
>{{{{[The VCO must be driven with a low noise low impedance voltage
>source so the VCO switching noise is not fed back to itself.  Your
>assertion is that the VCO output jitter is a linear function of time
and
>it goes to infinity as time goes on forever.  This is WRONG since such
>an open-loop system cannot be compensated by the closed-loop feedback.
>]}}}}=3D3D20
>
>
>However, placed in the PLL closed-loop environment, these large low
>frequency jitter components are suppressed by the PLL loop gain.  =
=3D3D20
>
>
>{{{{[This cannot be compensated. ]}}}}=3D3D20
>
>
>For
>an open loop, free running VCO, jitter from random noise sources is
>proportional to the square root of measurement interval or accumulated
>jitter interval (phase jitter).   =3D3D20
>
>{{{{[Again, low impedance and low noise power source]}}}}=3D3D20
>
>
>As for the temperature stability, my thinking is that in practice it is
>almost impossible to fully stabilize the temperature of a VCO and that
>there are internal thermal feedback mechanisms which  prevents full
>thermal equilibrium.  For example, if the temperature increases, the
>negative Tc for K may make the frequency go down a bit, temperature
>drops a bit later, K increases, and so on. =3D3D20
>
>{{{{[You are describing a thermal oscillation.  This means that you
have
>violated your thermal gain margin and phase margin.  This should not
>happen normally since environment temperature changes very slowly and
>the circuit responds much faster than the environment temperature
>change.]}}}}=3D3D20
>
>=3D3D20
>In practice, I had to phase
>lock the free running VCO output to make reasonably good phase noise
>measurements because of this.  If you have a better way of measuring
>open loop VCO phase noise, it would be interesting.  Frankly, I found
>VCO characterization to be non-trivial, so I'm listening...
>
>{{{{[We measure PLL jitter, and it is always stable -- no runaways.
>]}}}}=3D3D20
>
>
>Also, you mentioned "The increase in VCO jitter autocorrelation simply
>shows that the jitter event is random and non-repeating." what exactly
>does this mean? =3D3D20
>
>{{{{[I was talking about the DECREASE in VCO jitter autocorrelation
>simply shows that the jitter event is random and non-repeating.  If you
>add longer interval and the autocorrelation increases, you have low
>frequency power noise disturbances.  ]}}}}}=3D3D20
>
>
>The autocorrelation of white noise does not increase
>but is unity at the origin, and is it not also random and
>non-repeating???  =3D3D20
>
>
>{{{{[White noise has a special feature of self-autocorrelation.
]}}}}=3D3D20
>
>=3D3D20
>If I calculate the FFT on the variance record of a
>VCO, directly obtaining a power spectral density of the VCO jitter, I
>immediately see very large low frequency PSD jitter components.  And
>actually, I believe the jitter variance or autocorrelation record does
>go to infinity in the limit of ever increasing measurement intervals
>towards infinity for an open loop VCO.  =3D3D20
>
>
>{{{{[Bad design!  We do not see that.  Sorry.  ]}}}}=3D3D20
>
>
>BTW, can you please tone down your personally targeted comments.   I
was
>simply interested in what you were working on regarding the RMS jitter
>question...=3D3D20
>
>
>{{{{[I have work to do.  You are bugging me. ]}}}}=3D3D20
>
>
>Alfred P. Neves      <*)))))><{
>
>=3D3D20
>Hillsboro Office:
>735 SE 16th Ave.
>Hillsboro, OR, 97123
>(503) 679 2429 Voice
>(503) 210 7727 Fax
>=3D3D20
>Main Corporate office:
>Teraspeed Consulting Group LLC=3D3D20
>121 North River Drive=3D3D20
>Narragansett, RI 02882
>(401) 284-1827 Business
>(401) 284-1840 Fax=3D3D20
>http://www.teraspeed.com
>=3D3D20
>Teraspeed is the registered service mark=3D3D20
>of Teraspeed Consulting Group LLC
>=3D3D20
>
>
>-----Original Message-----
>From: Tang, George [mailto:George.Tang@xxxxxxx]=3D3D20
>Sent: Monday, March 19, 2007 12:31 PM
>To: Alfred P. Neves; Chris Cheng; si-list@xxxxxxxxxxxxx
>Subject: RE: [SI-LIST] Re: Jitter transfer vs. accumulation
>
>
>Alfred,=3D3D20
>
>First of all, temperature does not increase indefinitely; it reaches
>steady state equilibrium within an hour or two.  Once the temperature
>reaches equilibrium, your gain, thermal noise, and shot noise
>stabilizes, so the free running VCO jitter also stabilizes.  The 1/f^n
>dependency is not a function of time.  It is a function of all of the
>above except time.  I think you are very confused.  A closed-loop
>control system can only compensate a varying factor within a certain
>range.  If the open loop VCO jitter increases indefinitely, the closed
>loop system will not be stable since the feedback loop does not have
>infinite voltage range to compensate for a runaway parameter.  But this
>is certainly not what we observe in a locked PLL, which has stable
>jitter performance indefinitely over time.  Any kind of sanity check
>will tell you that a linearly increasing (up to infinity) open loop
>jitter of a VCO as a function of time will not yield a stable closed
>loop system with finite feedback in voltage and power.  The increase in
>VCO jitter autocorrelation simply shows that the jitter event is random
>and non-repeating.  It does not indicate that the jitter goes to
>infinity.  Again, you are very very confused. =3D3D20
>
>Without getting to the details, there are a number of specs which calls
>out 0.15UI total jitter.  At 12G, that is 12.5ps total jitter at BER of
>10^-15 or BER 10^-17.  You can calculate using the typical RJ, PJ, DDJ,
>and BUJ numbers to convince yourself that even at 500fs rms RJ, you may
>not pass the TJ spec.  You must not have kept up with the latest specs.
>
>
>=3D3D20
>George=3D3D20
>=3D3D20
>
>Note: Effective October 14, 2006, My LSI Logic Email address will
change
>to: george.tang@xxxxxxx
>
>Please update address books and email lists accordingly.
>
>
>-----Original Message-----
>From: Alfred P. Neves [mailto:al.neves@xxxxxxxxxxx]=3D3D20
>Sent: Friday, March 16, 2007 9:26 PM
>To: Tang, George; 'Chris Cheng'; si-list@xxxxxxxxxxxxx
>Subject: RE: [SI-LIST] Re: Jitter transfer vs. accumulation
>
>George,
>
>I disagree, a classic free-running ring oscillator (with a stable
>voltage control) VCO has 1/f^n noise components for  thermal noise and
>shot noise, and variation of gain versus temperature so the K factor is
>highly temperature dependant.  It is not wide sense stationary, the
>statistics do change as a function time.   That is why the VCO jitter
>autocorrelation record increases without bound as the record length
>increases.    There are several papers showing this, I also have
>empirical data illustrating this.
>
>I do agree with the jitter numbers you outlined.   BTW, what compliance
>specification calls for several hundred femto-second RMS jitter
numbers?
>Thanks.
>
>
>
>
>
>Alfred P. Neves      <*)))))><{
>
>=3D3D20
>Hillsboro Office:
>735 SE 16th Ave.
>Hillsboro, OR, 97123
>(503) 679 2429 Voice
>(503) 210 7727 Fax
>=3D3D20
>Main Corporate office:
>Teraspeed Consulting Group LLC=3D3D20
>121 North River Drive=3D3D20
>Narragansett, RI 02882
>(401) 284-1827 Business
>(401) 284-1840 Fax=3D3D20
>http://www.teraspeed.com
>=3D3D20
>Teraspeed is the registered service mark=3D3D20
>of Teraspeed Consulting Group LLC
>=3D3D20
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Tang, George
>Sent: Thursday, March 15, 2007 8:38 PM
>To: Alfred P. Neves; Chris Cheng; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Jitter transfer vs. accumulation
>
>
>Yes, statistical analysis really is the right way to analyze jitter.
You
>can plot the jitter of each edge as a function of time referencing to a
>certain edge.  Or, you can plot the histogram showing the distribution
>of a sample of edges, as on a scope.  But in this case, you have to
live
>with the scope internal time base jitter and the trigger input noise
>floor.  We have found that it is quite difficult to get PLL jitter
>number below 1 ps rms with this method.  WaveCrest is a very good tool
>for PLL jitter analysis with its RJ, PJ and DDJ analysis algorithms,
but
>again, we had a very tough time to reduce the equipment jitter noise
>floor to be below 1.3ps rms.  It's interesting that you bring up clock
>recovery units for this jitter measurement.  We have yet to find a CRU
>that has its own jitter noise floor below 300fs rms.  When the PLL that
>you are trying to measure has 1 sigma RJ in the range of 500fs, this
>300fs noise floor represents a significant error in the measurement.
>Only Agilent has several tools that can make jitter measurements in the
>range of 10fs to 100fs. =3D3D3D20
>
>A free running VCO may have jitter accumulation phenomenon initially
due
>to thermal reasons, but eventually it reaches steady-state operation.
>For PLLs, we have found the opposite.  An over-night data accumulation
>for the jitter measurement yields better results than a two-hour data
>accumulation.  And a two-hour accumulation on the 2nd day yields better
>results than a two-hour accumulation on the 1st day after steady-state
>temperature has been reached.  Running the test for a week yields even
>marginally better results than shorter tests. =3D3D3D20
>
>Of course, jitter measurements and calculations do not give the overall
>system margin until the variance and autocorrelation for the
independent
>random variables of the TX clock jitter and RX clock jitter are
>determined. =3D3D3D20 Without these, you only have partial data of the =
=3D
=3D3D
>overall
>picture. Further, if your system implements equalization for the data
>transmission, you must also add in the noise floor of the amplifiers
and
>the interference noise boosting due to adjacent channel cross-talk.
>There are quite a few factors to be considered in determining the
>overall margin of a serial data link. =3D3D3D20
>
>=3D3D3D20
>George=3D3D3D20
>=3D3D3D20
>
>Note: Effective October 14, 2006, My LSI Logic Email address will
change
>to: george.tang@xxxxxxx
>
>Please update address books and email lists accordingly.
>
>
>-----Original Message-----
>From: Alfred P. Neves [mailto:al.neves@xxxxxxxxxxx]=3D3D3D20
>Sent: Thursday, March 15, 2007 5:55 PM
>To: Tang, George; 'Chris Cheng'; si-list@xxxxxxxxxxxxx
>Subject: RE: [SI-LIST] Re: Jitter transfer vs. accumulation
>
>I think some of the issues discussed are better resolved by having a
>Stochastics Processes book by Popoulis nearby...
>
>=3D3D3D20
>There are 2 methods of measuring the N-clock jitter of a locked PLL,
one
>is measure one clock rising edge to the next edge (1 period jitter),
>sample this, then one edge to the 2 edges later, statistically sample
>again, then continue N cycles of jitter, calculating the RMS jitter for
>each N cycle jitter.   Any of the sampling scopes can measure this with
>a delay (Tek has a DL-11 delay), or you can measure this a bit easier
>with a Wavecrest instrument which directly measures N-clock jitter.
This
>measurement, as described, is self-referenced.  Another method of
making
>this measurement is using a recovered very low jitter clock. A
>statistical RMS versus time (or number of clocks)record can be built
>from the time differences between the rising edges of the PLL measured
>versus the recovered clock.
>
>This measurement relates to the autocorrelation record of the jitter
>process (Jan Wilstrup and Mike Li wrote some good papers on this back
in
>the late 90's), and some people call this "accumulated jitter",
although
>the Stochastic Processes books call this either Autocorrelation or
>Variance record.  There has been a lot of work to analyze this  (Steve
>Ambrose, Wavecrest corp, Teraspeed Consulting LLC) and develop useful
>methods for recovering data, and generating low jitter reference PLLs,
>for example.   You can immediately determine the loop and stability
>dynamics of a phase-frequency closed loop system like a PLL with this
>method.   The stationary properties of the jitter process becomes
>evident also, as would be expected with a locked PLL.  For all of these
>discussions I think it is important to state if the system is closed
>loop and has stationary statistics, or free runs and has non-stationary
>statistics like a free-running VCO. =3D3D3D20
>
>The typical log-log plot of this jitter sequence is y=3D3D3D3Dsqr(x) =
=3D3D
>looking,
>where the plot asymptotically looks like y=3D3D3D3Dconstant, it levels =
=3D
off
=3D3D
>due
>to the loop gain of the PLL. =3D3D3D20
>
>You can also make this measurement on a free-running VCO. The log-log
>plot of log(RMS) versus log(time) looks y=3D3D3D3Dmx+b, where m is >0.
This
>reflects that the RMS jitter accumulates as you count more cycles and
>that the jitter process is non-stationary such that the statistics of
>the process change over time and RMS jitter increases as time
progresses
>or measure the RMS jitter versus more N-clock cycles.    Interestingly,
>the PLL case is stationary so the jitter "stops accumulating" at a time
>interval related to PLL's loop bandwidth.  These RMS jitter versus
>N-clock cycle plots also directly correspond to the PLL's power
spectral
>density of the sidebands to the fundamental.
>
>What is also interesting is that the RMS jitter versus time plot can be
>compared with injecting periodic disturbances in the system, like
>modulating a sinusoidal waveform into the power supply port of a PLL,
so
>that you see a y=3D3D3D3D|cos(x)| envelope of the autocorrelation plot
(this
>process is called cyclo-stationary btw).   By taking the FFT of the
>autocorrelation sequence the power spectral density can be directly
>determined so you can actually determine the spectral energy of the
>jitter process itself.   We have also used the autocorrelation methods
>of optimization of VCO design, charge pump gain, and loop filter
>designs.
>
>I can bop out some good references regarding this.
>
>
>
>
>Alfred P. Neves      <*)))))><{
>
>=3D3D3D20
>Hillsboro Office:
>735 SE 16th Ave.
>Hillsboro, OR, 97123
>(503) 679 2429 Voice
>(503) 210 7727 Fax
>=3D3D3D20
>Main Corporate office:
>Teraspeed Consulting Group LLC=3D3D3D20
>121 North River Drive=3D3D3D20
>Narragansett, RI 02882
>(401) 284-1827 Business
>(401) 284-1840 Fax=3D3D3D20
>http://www.teraspeed.com
>=3D3D3D20
>Teraspeed is the registered service mark=3D3D3D20
>of Teraspeed Consulting Group LLC
>=3D3D3D20
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Tang, George
>Sent: Thursday, March 15, 2007 2:41 PM
>To: Chris Cheng; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Jitter transfer vs. accumulation
>
>
>I know you have a hard time understanding the fact that the test you
are
>describing is not a valid test, and the zero-phase-margin-phenomenon
>occurs only when you drive the power noise with too large an amplitude
>because you are controlling the gain of the input with your noise
>amplitude.  Your noise modulates the VCO directly and completely
>by-passed the phase comparator input all together.  The gain limitation
>of the phase comparator is taken out of the loop.  This has everything
>to do with the phase margin of the resulting circuit that you have
>created.  But you have a hard time understanding that.  Most newer PLL
>designs now have on-chip voltage regulator to filter and minimize the
>effects of power noise.  But no voltage regulator will survive the type
>of destructive tests that you do.  These tests do not happen with
normal
>operation.  I know you want a BMW that will survive a nuclear blast
>because you think BMWs have a lot of sheet metals on the outside.  But
I
>am sure that you will not be willing to pay for the price when they
make
>such a car for you.  Enough of these senseless arguing. =3D3D3D20 =
=3D3D3D20
>
>=3D3D3D20
>
>George=3D3D3D20
>
>=3D3D3D20
>
>Note: Effective October 14, 2006, My LSI Logic Email address will
change
>to: george.tang@xxxxxxx
>
>Please update address books and email lists accordingly.
>
>________________________________
>
>From: Chris Cheng [mailto:Chris.Cheng@xxxxxxxxxxxx]=3D3D3D20
>Sent: Thursday, March 15, 2007 1:54 PM
>To: Tang, George; si-list@xxxxxxxxxxxxx
>Subject: RE: [SI-LIST] Jitter transfer vs. accumulation
>
>=3D3D3D20
>
>Once again, I don't think you get what I am saying.
>
>Phase margin has NOTHING to do with the jitter accumulation test I am
>talking about. In fact the more phase margin you have (by over damping
>the loop) the more jitter you will accumulate due to power supply
noise.
>This has nothing to do with zero phase margin and I sincerely hope you
>don't have a design that has zero degree phase margin.
>
>The problem with the supply noise is as peripherals like DDR2/3 or CPU
>FSB is catching up with the Gb I/O's, their SSO harmonics are getting
>close to the band where the PLL vdd noise will severely impact the
>jitter accumulation. And there is not much you can filter if it happens
>inside the die.
>
>         -----Original Message-----
>         From: Tang, George [mailto:George.Tang@xxxxxxx]
>         Sent: Thursday, March 15, 2007 12:19 PM
>         To: Chris Cheng; si-list@xxxxxxxxxxxxx
>         Subject: RE: [SI-LIST] Jitter transfer vs. accumulation
>
>         Chris,=3D3D3D20
>
>         =3D3D3D20
>
>         I gave you the point that if you do a frequency sweep on the
>power noise of a PLL (not a VCO), you can induce a growing resonance of
>jitter eventually to the point that the PLL blows up (loses lock).  You
>can call this "jitter accumulation" if you wish.  This happens simply
>because the power noise modulates the VCO output.  The phase comparator
>at the PLL input that is trying to keep track and correct the phase
>difference between the VCO output and the RefClk input can no longer
>correct the phase difference.  This is exactly the same as if you do a
>frequency sweep at the RefClk input while the PLL power is kept noise
>free.  The phase comparator at a certain frequency will no longer be
>able to track and correct the phase difference between the VCO output
>and the RefClk input.  You need to analyze the phase margin and gain
>margin of the feedback control system to determine at what frequency
the
>system will blow up - when the phase margin becomes zero.  This is just
>a simple control system analysis, not the black magic arithmetic you
>described below.  You are also wrong about the DLL not blowing up.  The
>DLL also needs to meet the phase margin requirement.  With enough power
>noise at the right frequency, it will blow up, too.  You can reduce the
>gain of the circuit to improve margin, but that decreases the PLL
>performance.  The best way is to reduce the noise disturbance
frequency,
>or lower the RefClk jitter frequency - different approaches, same
>effect.  Like I said in the previous email, you have found a peculiar
>way to break the PLL, but the PLL is not designed to handle frequency
>sweeps.  I fail to see the significance of the stories that you
>describe. =3D3D3D20
>
>         =3D3D3D20
>
>         =3D3D3D20
>
>         George=3D3D3D20
>
>         =3D3D3D20
>
>         Note: Effective October 14, 2006, My LSI Logic Email address
>will change to: george.tang@xxxxxxx
>
>         Please update address books and email lists accordingly.
>
>=3D3D3D09
>________________________________
>
>
>         From: Chris Cheng [mailto:Chris.Cheng@xxxxxxxxxxxx]=3D3D3D20
>         Sent: Wednesday, March 14, 2007 10:53 PM
>         To: Tang, George; si-list@xxxxxxxxxxxxx
>         Subject: RE: [SI-LIST] Jitter transfer vs. accumulation
>
>         =3D3D3D20
>
>         If I correct my statement here : "You will see the AC noise
>induced on your PLL" to this :
>
>         "You will see the AC noise induced JITTER on your PLL" , will
>that make my statement better ?
>         I don't know how much more clear I have to explain my view
below
>that I am a true believer of phase noise accumulation due to power
>supply or substrate induced noise. Especially between the loop passband
>to the reference frequency and I have explain why below also. You can
>dig up many papers to study why this happen. Part of the originally
>attraction of DLL verse PLL is because it doesn't have the 1/s
>integration pole on the VCO, it is unconditional stable and therefore
>you can shift your loop bandwidth to as close to the reference
frequency
>as you want, thereby decreasing the jitter accumulation. But if you
drop
>it down to 1/1667 of the reference frequency, you make it even worst
>than what a PLL can do with proper loop dynamic.
>
>         As to the comment about bicycle helmet running into a car,
let's
>do the math here. Start off with how small a fraction of the cycle of
>jitter you can tolerate in radians. Divide by the VCO or VCDL gain in
>radians per volt (which should be a big number). That's how much noise
>you can live with in your VCO or VCDL per cycle. Now divide by how many
>cycles the jitter can accumulate until the loop can correct itself
(i.e.
>the ratio between the reference frequency and the loop bandwidth, to
>first order), and you will realize how little noise your VCO/VCDL can
>tolerate before your jitter budget is out of spec at the right
>frequency. And I can assure you if you hit it with the right frequency,
>you can knock your PLL or your DLL jitter budget out with a
surprisingly
>small amount of noise. Don't take my word, do the experiment yourself
on
>any PLL/DLL you get your hand on.=3D3D3D20
>
>         =3D3D3D20
>
>=3D3D3D09
>________________________________
>
>
>         From: Tang, George [mailto:George.Tang@xxxxxxx]
>         Sent: Wed 3/14/2007 8:13 PM
>         To: Chris Cheng; si-list@xxxxxxxxxxxxx
>         Subject: RE: [SI-LIST] Jitter transfer vs. accumulation
>
>         By now, I believe you agree that VCO jitter does not
accumulate.
>If I
>         modulate the VCO voltage with a 50mV low impedance power
source
>at a
>         fixed frequency, the power noise will be fixed at 50mV (again,
>low
>         impedance), therefore, the output jitter will be fixed at a
>certain
>         amount.  No accumulation there.  For the PLL, that is a
>different story.
>         There is the refclk input the PLL tries to lock to and there
is
>the
>         power noise disturbance.  Certainly, if you inject enough
>voltage noise
>         into power and do a frequency sweep, a wide bandwidth PLL will
>blow up
>         (loses lock) at some point.  But what is the point of this?
>Power
>         supply noises should be kept low, and they are usually
switching
>at a
>         fixed frequency, not a sweeping frequency.  If you take a
>bicycle helmet
>         and run it over with a car, you tell the helmet maker that it
>broke.
>         The helmet maker would tell you that the helmet is not
designed
>to
>         survive a car crash.  You simply found one way to break it.
I'm
>sure
>         there are a million different ways that will break it
also.=3D3D3D20
>=3D3D3D09
>         Thanks,
>=3D3D3D09
>         George
>=3D3D3D09
>=3D3D3D09
>         Note: Effective October 14, 2006, My LSI Logic Email address
>will change
>         to: george.tang@xxxxxxx
>=3D3D3D09
>         Please update address books and email lists accordingly.
>=3D3D3D09
>=3D3D3D09
>         -----Original Message-----
>         From: Chris Cheng [mailto:Chris.Cheng@xxxxxxxxxxxx]
>         Sent: Wednesday, March 14, 2007 7:21 PM
>         To: Tang, George; si-list@xxxxxxxxxxxxx
>         Subject: RE: [SI-LIST] Jitter transfer vs. accumulation
>=3D3D3D09
>         How does the jitter get accumulated ?
>         Let's do this experiment. AC isolate your PLLVDD, inject a
fixed
>         amplitude but varying frequency AC noise into your PLLVDD. In
>         particular, sweep it between the pass band of the loop filter
>and the
>         reference clock frequency. You will see the AC noise induced
on
>your PLL
>         supply get accumulated (bigger and bigger) as you sweep your
>noise
>         frequency from the refclk frequency down to your loop filter
>pass band
>         and graduately decrease as the phase detector finally be able
to
>correct
>         the phase error induced by the AC VDD noise.
>         The simple explanation is as AC power noise get injected into
>your high
>         gain VCO/VCDL, the phase error introduced is too fast (because
>the
>         modulation is beyond the pass band of the loop filter) to be
>instantly
>         corrected and required multiple cycles to accumulate enough
>charge in
>         the loop filter to pull back to the reference frequency. Hence
>jitter
>         accumulation.
>         BTW, I believe there are many papers descripting the above
>issue. And
>         believe it or not, I tested your company's first ever PLL
design
>and
>         wrote the first PLL filter app note for it while I was in
>another
>         computer company. The details are in there, I hope you can dig
>it up
>         again from somewhere :-D.
>=3D3D3D09
>         -----Original Message-----
>         From: Tang, George [mailto:George.Tang@xxxxxxx]
>         Sent: Wednesday, March 14, 2007 6:59 PM
>         To: Chris Cheng; si-list@xxxxxxxxxxxxx
>         Subject: RE: [SI-LIST] Jitter transfer vs. accumulation
>=3D3D3D09
>=3D3D3D09
>         Now that you specify VCO, so let's talk about that.  A VCO is
an
>         oscillating circuit in which the oscillation frequency is
>controlled by
>         the voltage.  Now if you have power noise (say sinusoidal),
you
>are
>         modulating the VCO so you have sinusoidal jitter at the
output.
>Where
>         does the "jitter accumulation" come from?  I do not understand
>the term
>         you use.=3D3D3D20
>=3D3D3D09
>         I believe you also did not understand Vinu and Paul's comments
>about
>         capturing the received data signals into logic levels and
>re-transmit
>         with a separate reference clk driven PLL.  The PLL has only
one
>input --
>         the ref_clk.  The PLL may have multiple phase output which can
>be used
>         to drive the phase interpolator input.  But there is still no
>jitter
>         accumulation there.  If you are talking about the recovered
>clock, yes,
>         the PLL jitter along with the CDR jitter plus the transmitter
>jitter
>         will add.  But some of this jitter will be filtered out by the
>next
>         stage PLL.=3D3D3D20
>=3D3D3D09
>=3D3D3D09
>=3D3D3D09
>         George
>=3D3D3D09
>=3D3D3D09
>         Note: Effective October 14, 2006, My LSI Logic Email address
>will change
>         to: george.tang@xxxxxxx
>=3D3D3D09
>         Please update address books and email lists accordingly.
>=3D3D3D09
>=3D3D3D09
>         -----Original Message-----
>         From: Chris Cheng [mailto:Chris.Cheng@xxxxxxxxxxxx]
>         Sent: Wednesday, March 14, 2007 6:14 PM
>         To: Tang, George; si-list@xxxxxxxxxxxxx
>         Subject: RE: [SI-LIST] Jitter transfer vs. accumulation
>=3D3D3D09
>         I am not sure about that.
>         I have to apologize I confuse everyone by using the term PLL
and
>you
>         will automatically interpret it as the PLL that is related to
>the Refclk
>         generation in the receiving side. But I think the term VCO is
a
>better
>         discription because it encompass both PLL and DLL. And VCO is
>where the
>         supply noise will be converted to phase noise (jitter
>accumulation).
>         The real question I have in the receiving area is the VCO in
the
>CDR of
>         the receiving chip.
>         As Vinu and Paul pointed out, if there is no Xtal input for
the
>Rx and
>         the clock is completely recovered from the data, we probably
>will agree
>         that PLL dynamics hold there.
>         However, even if we are talking about, and I think that's what
>Vinu was
>         refering to, a dual loop CDR with a seperate Rx clock PLL and
>use phase
>         interpolators for some kind of bang bang slave loop, you still
>need a
>         master phase generator using a DLL somewhere that will
generate
>those
>         multi-phases. And that DLL will have a VCO and it will suffer
>from VDD
>         or substrate induced phase noise. This is independent of
whether
>the
>         original refclk PLL dynamics. If you tell me that the
>multi-phase
>         generating DLL does not need to be held at 1/1667 bandwidth,
all
>my
>         confusion is cleared.
>=3D3D3D09
>         -----Original Message-----
>         From: Tang, George [mailto:George.Tang@xxxxxxx]
>         Sent: Wednesday, March 14, 2007 5:46 PM
>         To: Chris Cheng; si-list@xxxxxxxxxxxxx
>         Subject: RE: [SI-LIST] Jitter transfer vs. accumulation
>=3D3D3D09
>=3D3D3D09
>         Chris,
>=3D3D3D09
>         You sound very confused.  A receiver core has 2 types of
inputs
>--
>         reference clock input and RX data channel input.  You have
these
>2 types
>         of inputs mixed up completely.  Once you understand that they
>are
>         separate, most of your questions clear up =3D
automatically.=3D3D3D20
=3D3D3D09
>         Thanks,
>=3D3D3D09
>         George
>=3D3D3D09
>=3D3D3D09
>         Note: Effective October 14, 2006, My LSI Logic Email address
>will change
>         to: george.tang@xxxxxxx
>=3D3D3D09
>         Please update address books and email lists accordingly.
>=3D3D3D09
>=3D3D3D09
>         -----Original Message-----
>         From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]
>         On Behalf Of Chris Cheng
>         Sent: Tuesday, March 13, 2007 6:47 PM
>         To: si-list@xxxxxxxxxxxxx
>         Subject: [SI-LIST] Jitter transfer vs. accumulation
>=3D3D3D09
>         This stream of questions has been in my mind for the pass few
>years. And
>         every time I went to DesignCon I ended up with more and more
>questions
>         to myself rather than answers. So let me try to clear this up
>and let
>         everyone hammer me back down to the ground :-D.
>         Here it goes :
>=3D3D3D09
>         It is a well know phenomenon that PLL suffers from jitter
>accumulation.
>         i.e. Supply and substrate noise induced on the ultra high gain
>VCO
>         resulting in jitter. Many ways have been invented to combat
this
>         including PLLVDD filters, on-chip regulators and most
>importantly,
>         adjusting the PLL filter loop dynamics. It can be shown (and
>quite
>         intuitively) that when you decrease the lock time and increase
>the
>         tracking bandwidth, you allow the PLL to correct itself
quicker
>with the
>         induced jitter and thereby decreasing the peak to peak jitter.
>=3D3D3D09
>         It is also a well known phenomenon that in the presence of
input
>jitter,
>         the loop dynamics need to be adjusted to minimize the
>propagation of the
>         jitter. Worst there is a possibility of jitter peaking where
the
>jitter
>         may be amplified for a narrow band of frequency. It can also
be
>shown
>         (and again quite intuitively) that when you increase the lock
>time and
>         decrease the tracking bandwidth, you decrease the jitter
>tracking of the
>         PLL.
>=3D3D3D09
>         So from the above, it is clear that the solutions to the two
>problems
>         are contradicting each other. If you believe you have a
problem
>with
>         input jitter, you slow down your loop dynamics (or
over-damped)
>in your
>         PLL. If  you believe you have supply ripples or noisy
substrate,
>you
>         speed up your loop dynamics (well...at least make sure it is
>stable and
>         not under-damped).
>=3D3D3D09
>         To go deeper a little bit, what exactly are the input jitter
we
>are
>         talking about ? Well, let's use the convention jitter
>definitions, Tj,
>         Dj,Rj,DDj,ISI,DCD,Pj etc etc. For most of the multi-gigabit
>systems I've
>         seen, Dj seems to be the dominant component at the input in a
>system
>         environment. Within Dj, I believe the DDj part is relatively
>high-speed.
>         After all, your impulse response pre and post cursor dies down
>after a
>         few UIs and your alternating rise/fall edge clock (DCD)
happens
>in UI.
>         The benefit of the PLL dynamics has little or no effect on
such
>high
>         speed jitters. Most (but not all) of PLL loop dynamics are at
>least 20x
>         slower than the reference frequencies just to be stable. Any
>jitter
>         happens within a few cycles of the sampling frequencies does
not
>get the
>         benefit of low jitter transfer at any stable loop filter
>settings. So
>         now we have knock out the too big components of the input
>jitter, what's
>         left ? My guess is the true Rj AND the jitter induced from the
>transm
>         it circuit PLL (i.e. JITTER ACCUMULATION).
>=3D3D3D09
>         So when we are trying to fight the jitter transfer by dropping
>the loop
>         bandwidth, aren't we actually INCREASING the jitter
accumulation
>at the
>         transmitting end and we end up needing to cut the bandwidth
>downstream
>         to minimize jitter transfer ? Does the solution we are
>implementing
>         actually creates/worsen the problem ?
>=3D3D3D09
>         To every designers we see our own devil, I sure would not like
>to impose
>         my point of view on this issue on anyone who at least
understand
>my
>         points above. Whether you agree with me or not. However,
seeing
>the
>         latest FC or PCIe Gen II spec, it seems to be the group
thinking
>has
>         already been set to minimizing the jitter transfer is more
>important
>         than the jitter accumulation. In fact, I am not even aware of
>any jitter
>         accumulation spec in FC or PCIe (please correct me if I am
>wrong). The
>         fact that Fc is set to something like 1667th of the bit rate
>means the
>         PLL is way over damped.
>=3D3D3D09
>         This seems countered to my own experience of characterizing
>PLL's where
>         jitter accumulation almost always larger than true jitter
>transfer. I
>         have to qualify that with the jitter definition above. Slow
>non-high
>         speed input jitter transfer is what I am talking about. Dj's
and
>         specifically DDj input is big but not within the bandwidth of
>our
>         discussion here.
>=3D3D3D09
>         I know there are many smart brains that is responsible to come
>up with
>         this 1/1667 bit rate Fc, so somewhere along my logic I must be
>wrong.
>         Can someone point me to why jitter accumulation is less of a
>concern
>         than transfer in these standard ?
>=3D3D3D09
>         Chris
>
>
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