[SI-LIST] Re: Jitter transfer vs. accumulation

Alfred,=20

See comments in [[[[[ ]]]]]. =20

George=20


-----Original Message-----
From: Alfred P. Neves [mailto:al.neves@xxxxxxxxxxx]=20
Sent: Wednesday, March 21, 2007 11:07 PM
To: weirsi@xxxxxxxxxx; Tang, George; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Jitter transfer vs. accumulation

George,


>{{{{{Alfred made the initial postulate that open-loop VCO has rms=20
>jitter governed by his funny equation Y=3DmX + b, where Y is the rms=20
>jitter, X is the time duration of measurement, and m > 0.  This shows=20
>that as time goes to infinity, the rms jitter of the open-loop VCO also

>goes to infinity.

No George, this is not what I said.  It is the autocorrelation record of
the VCO that increases linearly on a log-log plot, where the axis are
log(RMS jitter) and log(time interval length), where this is not to be
confused with an RMS jitter or whether it is bounded or not. =20

[[[[[Amazing.  If your autocorrelation record for the open-loop VCO
looks like Y=3DmX + b, you have either invented a random-noise-free
environment (congratulations to you,) or your environment is so bad that
it is completely dominated by deterministic modulation so you cannot
take clean measurements at all.  My guess is that the latter case is the
truth.  ]]]]]]]=20


I already
provided numerous references regarding this and can also provide
numerous measurements for several VCO's to illustrate VCO RMS jitter
characteristics versus measurement interval.  We have used this analysis
100's of times for closed (and open loop) PLL analysis to determine the
PLL loop bandwidth and peaking in the PLL loop response. =20

[[[[[Like I said before, we do not see this problem in our measurements.
The VCO RMS jitter is bounded, and so is the PLL RMS jitter.  The RJ
distribution takes on a true Gaussian waveform.  In addition to that, we
test our communication channels (including TX, RX, &PLL) for weeks with
no errors.  All our measurements fairly closely match up with the system
BER predicted by the model simulation.  We do not see the problems that
you are fighting with.  ]]]]]=20


You can also
use this analysis to analyze jitter problems like spurious response due
to charge pump leakage, power supply junk like switching noise or HF
digital, XTALK in the substrate, SSO, and jitter multiplication from PLL
to PLL.  The basis for this analysis is work by John McNeil in
collaboration with Analog Devices in the mid 90's - have you read the
reference already provided, I can send you a copy if need be?   I didn't
originate the concept, just use the practical elements to analyze PLL's
and VCO's.  Before you belittle this, become dismissive, or make any
more personally targeted comments it may behoove you to do a bit of
homework.   And once again, you are asked to significantly raise the
level of your professionalism in your communications.  =20

> He further claimed that with the feedback loop of=20
>the PLL, the rms jitter became bounded.  You don't think Alfred was=20
>crazy enough to make the mistake of comparing phase jitter of VCO to=20
>the RMS jitter of the PLL, do you?  That will be comparing apples to=20
>bananas, let alone oranges

No, I did not say this either.  The reference was regarding the
autocorrelation record, NOT any comment regarding characteristics of VCO
RMS jitter.  A VCO has certain properties:   It has poor frequency
stability, it is temperature sensitive, it is not WSS (wide sense
stationary), it has a LOT of low frequency jitter due to numerous 1/f
noise sources, it also has unbounded RMS jitter, but the estimate of the
RMS jitter is difficult to measure since:   Measure the RMS of a VCO
over a certain time T, remeasure the RMS jitter later over the same time
interval and you will arrive at a different RMS number since it is not a
stationary process.   Sample size really has little to do with this.
BTW, do you have data on "stable" VCO's in terms of PPM frequency drift
versus time, after you claim the temperature stabilizes in 1-2 hours.

[[[[[If the RMS RJ of the VCO is unbounded, the closed-loop PLL will
never be fully stable since the feedback has finite correction
capability.  The only way the PLL can be fully stable is that the RMS
jitter of the VCO HAS TO BE BOUNDED.  We measure the PLL for say 20
minutes on day one and another 20 minutes on day 2 and day 3, and the
Peak-to-Peak jitter and RMS jitter for each day matches the results of
the other days down to 0.1ps range.  To say that the VCO and/or the PLL
has unbounded RMS jitter will be a tough tough sell, since you will
never be able to get this kind of repeatability otherwise.  ]]]]]]=20


NOW, place the VCO into a PLL loop that is locked on a stable input
signal, the VCO accumulated phase jitter  is shaped by the PLL loop
response.  The RMS RJ jitter measured (using some RJ-DJ extraction) will
be unbounded  - by definition.   =20

[[[[[Why?  What equipment do you use to give you such results? ]]]]]

The resulting PLL accumulated jitter,
phase jitter, or autocorrelation record will not continue to increase
past a value related to the PLL loops bandwidth, however (assuming the
loop is stable).  =20


[[[[[Phase jitter is bounded??  What equipment shows that! ]]]]]]

This is due to the intrinsic PLL loop gain. =20

[[[[[No, you are wrong, again.  Even when the PLL is in the locked
operation, the feedback can only correct the VCO jitter within the loop
bandwidth.  Beyond that, the feedback cannot do anything, period.  When
the overall PLL output RMS jitter is measured to be bounded across all
frequencies, then the VCO RMS jitter *must also be bounded across all
frequencies*. =20

On the other hand, phase jitter for a locked PLL is unbounded due to
probability of random events.  ]]]]]


My point is that the way to deal with both VCO's and the VCO-PLL
integrated loop is with autocorrelation analysis.  We have addressed a
lot of data recovery issues, PLL and VCO design issues using these
methods, solved a lot of problems.   Unfortunately, these methods are
not used that heavily (there is one exception in the industry however),
but we see value in the approach especially in regard to Chris's initial
email where you want to analyze peaking and jitter multiplication from
TX to RX, including models of the reference PLL or oscillator and signal
path.

[[[[[I do not doubt the validity of autocorrelation theories, but I
highly suspect that you have valid data to support your claims.
Especially when your environment gives you data in the form of Y =3D mX =
+
b.  ]]]]]



Alfred P. Neves      <*)))))><{

=20
Hillsboro Office:
735 SE 16th Ave.
Hillsboro, OR, 97123
(503) 679 2429 Voice
(503) 210 7727 Fax
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Main Corporate office:
Teraspeed Consulting Group LLC=20
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(401) 284-1827 Business
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of Teraspeed Consulting Group LLC
=20


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: Wednesday, March 21, 2007 8:29 PM
To: Tang, George; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Jitter transfer vs. accumulation


George, thanks for the reply.
At 05:02 PM 3/21/2007, you wrote:
>Steve,
>
>Please see comments in {{{{{ }}}}} below.
>
>
>George
>
>
>snip
>-----Original Message-----
>From: steve weir [mailto:weirsi@xxxxxxxxxx]=3D20
>Sent: Tuesday, March 20, 2007 4:10 AM
>To: Tang, George; Alfred P. Neves; Chris Cheng; si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Re: Jitter transfer vs. accumulation
>
>George, please correct me if I am wrong, but I believe:
>
>1) That the inverter gain K is both temperature and supply voltage=20
>dependent.
>
>{{{{{True, not a function of time. }}}}}
>
Good.  Then do we also agree that when the supply voltage and=20
temperature both vary with time that the gain does as well?  If not why?


>2) That even in an isothermal, constant supply, and zero noise =
Vref=3D20=20
>environment, running open-loop that in the limit any single VCO=3D20=20
>output interval can vary from epsilon*ring_stages to approximately=3D20 =

>Vcc/Vths_nom*UI*ring_stages.
>
>{{{{{You CANNOT rewrite the laws of physics with your funny formula.=20
>The input sensitivity (in mV) is not proportional to VCC voltage nor=20
>inversely proportional to Vth.  Throwing such formulae around does not=20
>fool people into believing you.  }}}}}

George there is no attempt to "fool people".  Please keep the=20
discussion on a professional level.

The minimum period for one inverter in the presence of a large enough=20
shot noise pulse is the inverter minimum delay time epsilon, is it not?
An arbitrarily large noise shot pulse can only defer a transition by=20
a maximum amount of time.  If you object to the approximation of=20
Vcc/Vths I am open to discussion of alternative approximations.


>Maybe I don't understand what you mean by
>
>"My assertion is that when temperature,
>voltage, low noise level and fixed noise frequency parameters are all=20
>in steady-state condition, the open-loop VCO output jitter shall be=20
>constant."
>
>{{{{{The output RMS jitter shall be constant.  When we talk about PLL=20
>or VCO jitter, we usually talk about the RMS jitter.  Phase jitter is=20
>meaningless unless you specify the sample size.  }}}}}
>
>
>That sounds like Dj induced from power supply feedback.
>
>
>{{{{{Whatever the cause, the result is the same.  }}}}}

OK I think we agree there is a big difference between peak jitter and=20
RMS jitter.  So, I think we can put that aside and concentrate on RMS
jitter.


>My interpretation is that even in this pristine environment of a=3D20=20
>perfect power supply the oscillator exhibits unbounded Rj.  If it =
is=3D20

>bounded, what limits it?
>
>{{{{{Alfred made the initial postulate that open-loop VCO has rms=20
>jitter governed by his funny equation Y=3DmX + b, where Y is the rms=20
>jitter, X is the time duration of measurement, and m > 0.  This shows=20
>that as time goes to infinity, the rms jitter of the open-loop VCO also

>goes to infinity.  He further claimed that with the feedback loop of=20
>the PLL, the rms jitter became bounded.  You don't think Alfred was=20
>crazy enough to make the mistake of comparing phase jitter of VCO to=20
>the RMS jitter of the PLL, do you?  That will be comparing apples to=20
>bananas, let alone oranges.
>
>My claim is that both VCO rms jitter and PLL rms jitter are bounded,=20
>and the closed-loop feedback circuit simply attenuates the open-loop=20
>rms jitter.  Both circuits have unbounded phase jitters.  }}}}}

So it sounds to me that we agree that Rj is unbounded.  My experience=20
agrees with Al's assertion that due to Rj, RMS jitter does creep=20
upwards with time.  This is the evil of the 1/f noise corner=20
exhibited by every DC amplifier I have encountered.  If noise density=20
/ square root frequency were the RMS value wouldn't creep.  What is
wrong here?

I have to agree with you that an indefinite divided by a definite is=20
still indefinite.  Al will have to address whether he was saying that=20
feedback bounds peak jitter, and if so why.



>In my world, ( which may be perverse ) the only way that we get to=3D20 =

>bound Rj is to bound the number of UIs, and we don't get to do =
that=3D20=20
>until we close the feedback loop.
>
>
>{{{{{Sorry, another funny theory of yours.  RJ is a statistical=20
>probability.  Bounding the number of UIs does not bound the=20
>peak-to-peak RJ.  Closing the feedback loop does not bound RJ p-p. =20
>}}}}}
>

I acknowledged that I mispoke on this in my private e-mail to=20
you.  The likelihood that an event outside some magnitude will occur=20
shrinks with reduced exposure.  Applying feedback cannot reduce the=20
limit which remains indefinite.  It does however effectively reduce
sigma.

>In my mind this goes back to=3D20
>Chris' issue which is that from the loop cut-off up to 1/UI the =
VCO=3D20=20
>accumulates phase error based on thermal, power supply noise, and=3D20=20
>reference voltage noise disturbances with little or no=3D20 =
attenuation.

>It is only well within the closed loop B/W that=3D20 feedback =
diminishes=20
>those error terms WRT the apparent reference=3D20 timing source.  Is =
this

>incorrect?
>
>
>{{{{{No.  Phase jitter is always accumulated regardless open-loop or=20
>closed-loop.  Closing the loop does attenuate the phase error within=20
>the bandwidth, but RMS RJ does not go to zero.  }}}}}
>

We agree that feedback cannot drive jitter to zero.  I remain at odds=20
with your blanket assertion that phase jitter accumulates in a closed=20
loop as well as an open loop.  Jitter is a noise term, and all my=20
references state that a feedback loop works to reduce noise terms of=20
the elements within the loop.  Do you have a reference as to why this=20
would not be so in this situation?

It appears we agree that the loop acts to reduce phase error which is=20
what we care about and where Chris' complaint came from.  We appear=20
to also agree that as we slide down the GBW curve the amount of=20
correction shrinks.  Do we agree that well above the 0db crossing the=20
loop does almost nothing to adjust the VCO phase to match the=20
incoming data stream?  If we agree then I think Chris' point is=20
made.  If we don't, I would like to know why.  It may be for the=20
particular standards that Chris is unhappy about that other concerns=20
drove the cut-off frequencies selected.  But from the narrow=20
perspective of the PLL bandwidth impact on CDR function I see his point.

>If so, why?  Absent feedback, I=3D20
>expect the each inverter in the oscillator to exhibit 1/f noise =
like=3D20

>any other amplifier no matter how clean the power supply is.  Do =
you=3D20

>agree?  If not, why?
>
>{{{{{Sure.  But with feedback, the same is still true that the random=20
>noise is still present.  That is not the point of the argument.  }}}}}
>

I am not sure if we agree that feedback attenuates all types of noise.
Do we?


>I agree that designing a stable VCO and feeding it with clean low=3D20=20
>impedance power are important towards achieving low jitter.  But I=20
>am=3D20 having difficulty following the apparent idea that achieving=20
>those=3D20 goals eliminates jitter components as opposed to reducing =
them

>to=3D20 small values.  Is there a conflict between semantics of "very=20
>small"=3D20 and "zero"?
>
>
>{{{{{I never said that jitter can be eliminated.  I only said that RMS=20
>jitter is bounded for both VCO and PLL.  Alfred made the assertion that

>VCO has unbounded rms jitter, but PLL has bounded rms jitter.  The=20
>funny equations you guys put out do not help with your arguments at=20
>all. }}}}}
>

Al is very capable and knowledgeable in this area.  I do not speak=20
for him.  It would be a lot easier to reach a common understanding if=20
you could tone down the open hostility.


>Regards,
>
>
>Steve.
snip=20

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