[SI-LIST] Re: DDR SDRAM signal routing
- From: Alan Hilton-Nickel <alan@xxxxxxxxxxxxxxxxx>
- To: tbiggs@xxxxxxxxxxxxxxxxxxxxx
- Date: Mon, 08 Nov 2004 23:26:06 -0800
Y'know, I would back the suggestion that simulations are not totally
necessary, given that you are putting all your memories down on the
board (no modules). This design just isn't that complicated and the
controller isn't that flexible.
At 2 ranks of DDR I at 167 MHz, this design is not really pushing the
envelope. You do need access to a 2D simulator to plan your stackup and
geometry. If you don't even have access to a 2D simulator, you can work
with your board manufacturer (and their 2D simulator) to set up the
geometries to get your characteristic impedance, and to set trace
separations to minimize crosstalk. With 72 data lines, though, you will
have limited space, so you'll just have to do your best to keep bytes
separated and to provide extra separation for strobes and clocks.
You will need to know enough to control your topologies, and to avoid
dumb mistakes like crossing planes splits. The banks will need to be
back-to-back, meaning parts on both sides, and you will need to do some
bit-swapping to keep the routing simple. You will also need to do some
spreadsheet work to make sure you have the correct trace lengths - as
you've correctly mentioned, the trace lengths for data and address will
be different, as will the loadings (18 loads on ADDR/CLK vs 2 on
Data/Strobe). You'll have to take that into account.
Consider your power supply distribution very carefully. You have 72 data
lines potentially switching at the same time, so plenty of opportunity
for SSO.
Looking at the chip spec, I see no spec for output impedance. During
bringup, you'll need to play with your terminations to reduce
reflections. Then you can play with the timing registers to get ideal
setup for the memories you are using. I would budget for a second board
spin, but no more.
If you were wanting to use memory modules with multiple configurations
and chip combinations, or if you were wanting to go at, say, 300 MHz,
you would need to simulate. But since the topologies are fixed and
controlled by you, I think you have more leeway than a lot of us usually do.
Your worries with not doing the simulations are going to center around
ISI. You would probably want to get an eye diagram using several random
and not-so-random data patterns, and possibly introducing some package
inductance for SSO and some random and deterministic jitter. You would
also want to simulate your topologies and loadings to make sure you get
the expected waveforms and delays for fast and slow silicon. As others
have pointed out, simulations will buy you an added layer of confidence.
That extra confidence could come at the expense of days to weeks of
simulation time, in which you could spin the board two or three times.
Good luck,
Alan
Tom Biggs wrote:
>I'm going to play devil's advocate here just to get people thinking.
>(Note that I simulate the DDR designs I've done).
>
>Ed says "The driving force behind all this is time to market and system
>reliability."
>
>There is one other force: cost. These days we can be easily outsourced
>if we are too expensive to our bosses.=20
>
>How many IBM PowerPC 440GX (now AMCC's chip) designs have been done? How
>many times have people simulated them and come up with design guidelines
>that will work? Yes, many of these designs are different from each
>other, but I would bet that many of them are EXACTLY the same. Do we
>need 100 engineers to simulate the exact same thing 100 times to come up
>with 100 identical sets of routing rules?=20
>
>If AMCC ran lots of simulations, then came out with a set of strict
>routing rules for some typical embedded 440GX applications, then someone
>should be able to design a board with these rules and not have to run
>simulations. Reliability should be fine if they do their job right, time
>to market will be short, and cost will be low.
>
> -tom
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Ed Sayre III
>Sent: Monday, November 08, 2004 9:33 AM
>To: pm_norge@xxxxxxxxxxx
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: DDR SDRAM signal routing
>
>
>Peter,
> You NEED to run simulations. I have worked on DDR SDRAMs
>architectures=20
>for many years now and every one was slightly different. You can
>benefit=20
>greatly from simulations since it generates your skew budget, component=20
>placement and proper termination among other design points. If you=20
>management tells you that they are willing to spend the money on
>repeated=20
>turns, where you may or may not find the right answer, then you are
>wasting=20
>your money. Either hire a consultant with experience in the area of DDR
>
>memory or develop your own in house expertise. There are many people
>and=20
>products available right now. The driving force behind all this is
>time=20
>to market and system reliability.
>
>Good luck
>-Ed Sayre
>
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> NORTH EAST SYSTEMS ASSOCIATES, INC
> -------------------------------------=20
>
> "High Performance Engineering & Design"
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Dr. Edward Sayre 3rd e-mail: esayre3@xxxxxxxx
> NESA, Inc. http://www.nesa.com/
> 5 Lan Drive, Suite 200 Tel +1.978.392-8787 x 218
> Westford, MA 01886 USA Fax +1.978.392-8686
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>
>
>At 09:32 AM 11/8/2004 +0000, you wrote:
>
>
>>I have been designing different kinds of electronic products, but never
>>
>>
>
>
>
>>a DDR SDRAM interface with 16 memory chips (MT46V64M8, 512Mb chip,=20
>>8-bit @ 167MHz)and 2 ECC chips (same type).
>>
>>Between the processor (IBM PowerPC 440GX) and memory chips there are=20
>>only the transmission lines and series termination resistors (25Ohm=20
>>close to the processor). I do not have the possibility to run=20
>>simulations, so it's learning by doing.
>>
>>The data lines are around 60-70mm and the address line around 250mm!!!=20
>>long. I'm afraid I will get serious SI problems with this=20
>>configuration. I read some Appnotes but I could really use some help=20
>>
>>
>>from experienced SI designers. What kind of termination do I really=20
>
>
>>have to implement and what do I have to look out for?
>>
>>Thanks in advance
>>Peter
>>
>>_________________________________________________________________
>>Last ned MSN Messenger gratis http://www.msn.no/computing/messenger -=20
>>Den korteste veien mellom deg og dine venner
>>
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