[SI-LIST] Re: DDR SDRAM signal routing

  • From: Guasti Giovanni <Giovanni.Guasti@xxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Wed, 10 Nov 2004 10:52:40 +0100

Hi people,
just to say that if we should observe ALL the rules and guideline of
application notes, we could  seldom succeed in making a working pcb. =
that cases in which it's impossible to observe a guideline, I think
simulating is the only way to be confident in the good result.
And more, sometimes it happens to read about really strange =
constranits, for
example, I remind of a GTL bus at 400MHz that had to be traced with NO =
than 0.6mm length difference between each line (from a very popular
microprocessor design guide).=20
0.6mm are about 4ps of delay: could a timing budget be so critical?

-----Messaggio originale-----
Da: giancarlo guida [mailto:gguida@xxxxxxxxxx]
Inviato: mercoled=EC 10 novembre 2004 9.46
A: hmurray@xxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: Hal Murray
Oggetto: [SI-LIST] Re: DDR SDRAM signal routing

Hi Hal and others,
I read this interesting post
and I believe there is a very interesting basic question behind the =

At the end of the day it seems we are in fornt of the doubt
should one follow the Appnote  and/or guideline
or make simulations?

I have no doubt that the Appnote and guideline
can be very accurate and give good suggestion
but every PCB is a unique "world"
where the suggestion you got from Appnote could work perfectly
but could also fails.

A golden rule cannot be golden enough to not be verified in your real =
... to make such a verification, I would say that a good simulator is =
ultimate solution.

Along others advantages, a direct usage of a simulator will allow to =
deep knowledge of your application
and short the design cycle by an unexpected ratio.

It has been demonstrated the ROI of a good simulator is practically


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