[SI-LIST] Re: DDR SDRAM signal routing
- From: "Chris McGrath" <chris.mcgrath@xxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 10 Nov 2004 08:32:36 -0800
I'll just chime in and say that we have a design with the 440GX with ten =
memory chips (same Micron chips but 16 bits wide, so the chip count is =
lower) and it is completely embedded memory (no DIMM). Due to time =
constraints, we had an external company simulate the interface but for =
reasons that I can share privately (not on the list) we ended up redoing =
them all ourselves and had to change the termination topology for =
something that simply considering SI does not get you- maximum timing =
margins.
If you are just doing a DIMM design, the app notes will take you most of =
the way there but if you have not dissected the 440GX memory controller, =
I encourage you to spend some serious time understanding it. We have an =
internal ADIC paper written on it that is over 100 pages long because =
the IBM/AMCC application documentation was insufficient (at the time, =
anyway) to guarantee high reliability in systems such as ours. In a =
nutshell, there are many knobs to turn in that chip to tune the timing, =
so the SI is one piece of it. Different termination topologies have =
been shown in simulation and subsequently in lab verification to affect =
overall timing margins as well as the variance in timing margins between =
boards. We have lots of data to support this and I hold this up as an =
example of how SI and timing work hand-in-hand and we have learned =
through experience that "optimizing" is a term that must be applied to =
the system and not just one element of the design.
We did rigorous simulations on that interface and beat the heck out of =
it in the lab (including performance testing in the thermal chamber and =
having software do active calibration of the delay lines at boot time), =
so simulation was only one piece of the design effort. =20
The bottom line is that if you are not in a high reliability system and =
you are using a DIMM, you may be able to cut some corners on SI but you =
may pay for them later depending on the rigor of your testing or, worse, =
the rigor of your customers' environments. =20
-Chris
> -----Original Message-----
> From: Peter M=FCller [mailto:pm_norge@xxxxxxxxxxx]=20
> Sent: Monday, November 08, 2004 4:32 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] DDR SDRAM signal routing
>=20
>=20
> I have been designing different kinds of electronic products,=20
> but never a=20
> DDR SDRAM interface with 16 memory chips (MT46V64M8, 512Mb=20
> chip, 8-bit @=20
> 167MHz)and 2 ECC chips (same type).
>=20
> Between the processor (IBM PowerPC 440GX) and memory chips=20
> there are only=20
> the transmission lines and series termination resistors=20
> (25Ohm close to the=20
> processor). I do not have the possibility to run simulations, so it's=20
> learning by doing.
>=20
> The data lines are around 60-70mm and the address line around=20
> 250mm!!! long.=20
> I'm afraid I will get serious SI problems with this=20
> configuration. I read=20
> some Appnotes but I could really use some help from experienced SI=20
> designers. What kind of termination do I really have to=20
> implement and what=20
> do I have to look out for?
>=20
> Thanks in advance
> Peter
>=20
> _________________________________________________________________
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> korteste veien mellom deg og dine venner
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