[SI-LIST] Re: DDR SDRAM signal routing
- From: steve weir <weirsp@xxxxxxxxxx>
- To: tbiggs@xxxxxxxxxxxxxxxxxxxxx, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 08 Nov 2004 21:32:26 -0800
Tom, I think your points are valid...but, the whole issue of simulation is
what assumptions were used. If in fact there is already a simulation that
includes the same configuration, and relatively close geometry then a
science project can be avoided. But if any: the memory mfg is different,
the device count is different, or the topology is significantly different
than what simulations were run, I believe there is either homework to do or
some prayer that is in order. If there is not sufficient value to justify
the engineering then there are alternatives such as using a design that is
completely canned.
How expensive is a flaky CPU subsystem?
Regards,
Steve.
At 10:11 AM 11/8/2004 -0800, Tom Biggs wrote:
>I'm going to play devil's advocate here just to get people thinking.
>(Note that I simulate the DDR designs I've done).
>
>Ed says "The driving force behind all this is time to market and system
>reliability."
>
>There is one other force: cost. These days we can be easily outsourced
>if we are too expensive to our bosses.=20
>
>How many IBM PowerPC 440GX (now AMCC's chip) designs have been done? How
>many times have people simulated them and come up with design guidelines
>that will work? Yes, many of these designs are different from each
>other, but I would bet that many of them are EXACTLY the same. Do we
>need 100 engineers to simulate the exact same thing 100 times to come up
>with 100 identical sets of routing rules?=20
>
>If AMCC ran lots of simulations, then came out with a set of strict
>routing rules for some typical embedded 440GX applications, then someone
>should be able to design a board with these rules and not have to run
>simulations. Reliability should be fine if they do their job right, time
>to market will be short, and cost will be low.
>
> -tom
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Ed Sayre III
>Sent: Monday, November 08, 2004 9:33 AM
>To: pm_norge@xxxxxxxxxxx
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: DDR SDRAM signal routing
>
>
>Peter,
> You NEED to run simulations. I have worked on DDR SDRAMs
>architectures=20
>for many years now and every one was slightly different. You can
>benefit=20
>greatly from simulations since it generates your skew budget, component=20
>placement and proper termination among other design points. If you=20
>management tells you that they are willing to spend the money on
>repeated=20
>turns, where you may or may not find the right answer, then you are
>wasting=20
>your money. Either hire a consultant with experience in the area of DDR
>
>memory or develop your own in house expertise. There are many people
>and=20
>products available right now. The driving force behind all this is
>time=20
>to market and system reliability.
>
>Good luck
>-Ed Sayre
>
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> NORTH EAST SYSTEMS ASSOCIATES, INC
> -------------------------------------=20
>
> "High Performance Engineering & Design"
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Dr. Edward Sayre 3rd e-mail: esayre3@xxxxxxxx
> NESA, Inc. http://www.nesa.com/
> 5 Lan Drive, Suite 200 Tel +1.978.392-8787 x 218
> Westford, MA 01886 USA Fax +1.978.392-8686
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>
>
>At 09:32 AM 11/8/2004 +0000, you wrote:
> >I have been designing different kinds of electronic products, but never
>
> >a DDR SDRAM interface with 16 memory chips (MT46V64M8, 512Mb chip,=20
> >8-bit @ 167MHz)and 2 ECC chips (same type).
> >
> >Between the processor (IBM PowerPC 440GX) and memory chips there are=20
> >only the transmission lines and series termination resistors (25Ohm=20
> >close to the processor). I do not have the possibility to run=20
> >simulations, so it's learning by doing.
> >
> >The data lines are around 60-70mm and the address line around 250mm!!!=20
> >long. I'm afraid I will get serious SI problems with this=20
> >configuration. I read some Appnotes but I could really use some help=20
> >from experienced SI designers. What kind of termination do I really=20
> >have to implement and what do I have to look out for?
> >
> >Thanks in advance
> >Peter
> >
> >_________________________________________________________________
> >Last ned MSN Messenger gratis http://www.msn.no/computing/messenger -=20
> >Den korteste veien mellom deg og dine venner
> >
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