[SI-LIST] Re: Article discussion on bad packages
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: chris.mcgrath@xxxxxxxx
- Date: Wed, 29 Dec 2004 13:00:35 -0500
Chris
Both of the points that you make are dead on. I especially like your
following comment:
>having program folks understand this type of issue allows us to better
>quantify risk to
>programs when choosing a vendor if they better understand the shades of
>grey. For instance, if vendor A can better describe their SI design and
>testing for a chip and produce good PCB design use guidelines when
>compared to vendor B, then vendor A is more desireable.
>
>
In a perfect engineering driven world, this is the optimal outcome.
However, it is my experience that many chips, COTS, custom, FPGA and
ASIC are chosen with overall cost as an overriding factor. It is often
hard to figure in the probablity of design failure, until it happens at
least once. At that point it is often too late. I've seen many choices
for ASIC foundry made simply because of the design team's familiarity
with one particular design flow.
Also, it is not necessarily true that Vendor A has a better chip, just
because they have the information that you need. Digging into many PCB
design guides will often expose the man behind the curtain as being just
a Carny, or expose the methodology as lacking. However, having the
information with which to make an informed engineering decision is
always better than having no information at all. Run like the wind from
vendors who can supply no SI or power integrity (PI) information
whatsoever, and have no clue what you're asking for. Too many vendors
see SI as being complete when they deliver a poorly constructed IBIS
model to their customers.
Intel, Sun, Cisco, IBM and many others have excellent SI and PI design
teams, because they have seen the failures and seen the light.
scott
--
Scott McMorrow
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