[SI-LIST] Re: Article discussion on bad packages
- From: zhangkun 29902 <zhang_kun@xxxxxxxxxx>
- To: scott@xxxxxxxxxxxxx
- Date: Thu, 30 Dec 2004 08:20:22 +0800
Dear all
I have read some mails in this thread. I guess that the center topic is to use
what kind of model to simulate. As to my experience, in power integrity(PI)
analysis, the simulation need not to be very exact, which is impossible. If the
IC vender could provide some model for the package coupling and IC buffer power
consuming, it is very helpful for SSN analysis. However, I could not get enough
information now. Now connector vender could provide good model. It is very
helpful that if the IC vender could provide similar model.
For instance, I am analyzing a SSN problem in FPGA. There are 1 clock and 32
data signal. When the 32 data signal change from 0 to 1 (or 1 to 0), there is a
spike of 1V on the clock signal. It is very dangerous. In order to cut the
spike, we have to make 16 data change at one time and the other 16 change after
4ns. Therefore there are two spike of 600mV on the clock and the timing is
getting worse. In the datasheet, there is only "there should not be more than
20 buffer changing at one time in one bank." It is too simple.
Again, the model provided by IC vender need not to be too exact, that is
impossible for both the IC vender and the simulation. However, the engineer at
PCB level need more information for successful product. The current model and
information is not enough. IBIS is only for buffer. The model for package is
also necessary for coupling and SSN analysis.
Best Regards
Zhangkun
2004.12.30
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