[SI-LIST] Re: Article discussion on bad packages

Happy New Year to all!

Having gone through the collection of messages to this point, I have a few
questions I'd like to raise:

1) How are people accounting for the effects of on-die decoupling in their
analyses?  We can analyze the power delivery capbilities of the package, but
part of the power delivery system is implemented by on-die decoupling, isn't
it?  How do folks go about extracting die parasitics and incorporating them
into their PDS analyses?

2) It seems to me that the combination of on-die and [optionally] on-package
decoupling makes the package/die PDS self-sufficient above some frequency.
If we look at the board PDS, the target PDS impedance requirements would
therefore increase with frequency.  The rolloff (or rollup, if you prefer)
of target impedance with frequency would be design-specific, and, I believe,
complex to determine, but would nonetheless serve as a design requirement
for the board's PDS at that point.

My question here - does anyone else think this would be a possible and
reasonable method for documenting a chip's high speed current requirements?
I suggest we leave FPGAs out for the moment, since their requirements will
be design specific.  Could we document PDS impedance/frequency profiles for
standard components, and use that information to segregate some of the high
speed signaling and PDS design tasks?

Comments are welcome and appreciated.

Todd.

Todd Westerhoff
High Speed Design Specialist
Cisco Systems
1414 Massachusetts Ave - Boxboro, MA - 01719
email:twesterh@xxxxxxxxx
ph: 978-936-2149
============================================

"Always do right.
 This will gratify some people and astonish the rest."

- Mark Twain

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