[PCB_FORUM] Re: Removing unused pad rings on inner layers DURING design...
- From: chris.ball@xxxxxxxxx
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Fri, 1 Apr 2005 17:30:33 -0400
Hi Kevin-
VB98.2 was the last 'great' Veribest, IMHO. Still ran over Microstation.
They revised it drastically shortly before becoming Mentor.
Pads are very different. You have a function, 'Pads Processor', which you
can use to add/delete/modify pads by pincode, padcode, and/or layer. It
knows SMT from througholes, and connected from unconnected.
It has some real advantages, like what we're talking about, but maybe some
disadvantages too.
When boards were mostly throughole, it was great 'cause you could build
your parts with no pads, just pins, and then add pads based on single
-sided or plated-thru tables... you didn't need two parts in your library
to get the right annular ring for the process. Also works well with wave
vs' reflow SMT pads and soldermask openings for screened mask vs. LPI or
dryfilm. Kept your library size down (but made for a lot of pin table
work).
I don't remember the disadvantages at the moment, but I'm thinking there
were some....
You could build your vias with outer only or all pads, depending on how you
preferred to work. Then add or delete as often or infrequently as you
chose.
For applications like Austin is referring to, I'm sure a great deal of
planning goes into what's escaping on which layer, so I'd think you
wouldn't just miss a pad from the get-go. You're right in that if you have
to add a pad later, you might have to move a trace or regen a plane, but
such is life... right? A change is a change.
I remember that the biggest obstacle in the migration from VB to Expedition
was defining the padstacks for your components... The main reason we stayed
back was the loss of Microstation. Made working with mech. designers a
breeze, as well as all your documentation.
We do a lot of odd shaped boards tightly integrated into bizarre 3D pkgs...
and I had complete 3D output of my design with a button click. Real sexy.
With VB, I can go from placement to a 3D Catia assembly containing my board
in a heartbeat (or 70 or so). I know all that is possible one way or
another with Cadence, but we don't have the goods in place today.
Can you tell I miss it? I'm starting to not hate Cadence, so progress is
being made...
Happy Friday,
-Chris
Kevin McCowan
<kmccowan@xxxxxxxxxxxxxx> To:
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Sent by: @VALSMTP Subject:
[PCB_FORUM] Re: Removing unused
pad rings on inner
layers DURING design...
04/01/2005 09:44 AM
Please respond to
icu-pcb-forum
I've been following this thread and it is very interesting.
My only issue, and I have done this before, is what happens
when you need to add a pad back and there is no longer
any room for it? The pads are needed to keep this situation
from arising. I also was using the Mentor (veribest) tool at
the time, but I cannot say it was easy by any stretch of
the imagination. Maybe they have added a way to do it that
wasn't there when I used the tool. (It's been 2 years.)
When I did it the tool had a feature to remove unused
pads after it was routed, but before creating gerbers.
It is possible to set up the rules to plan for the eventual
removal of the pads, but is it a good idea?
Kevin McCowan
Sr. PCB Designer
TSI Telsys
Musetti, Carl wrote:
> Really Good idea!
>
> I'm sure most of you are aware of this but when you talk about
making a pad size the size of the drill you need to consider
that pad size as the actual drill bit size not finished
drill + the
standard manufacturing tolerances. Then you would apply that
minimum
clearance to that pad shape.
>
> My 2 cents
>
> Carl
>
> -----Original Message-----
> From: MAILER-DAEMON@xxxxxxxxxxxxx [mailto:MAILER-DAEMON@xxxxxxxxxxxxx]
> Sent: Thursday, March 31, 2005 5:06 PM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: Removing unused pad rings on inner layers
> DURING design...
>
>
> OK, so what if you defined the via "pad" to be the hole size. Then
> each via you routed to on a certain layer, where you really wanted a
> full size "pad", you could add a circular filled shape at the via site.
> It's still manual, but a lot less work than messing with multiple via
> padstacks.
> And ... I'm guessing that if you were proficient in skill, a program
> could be written to add the little circular shapes wherever a via had a
> connection made.
>
> -----Original Message-----
> From: David Greig [mailto:david@xxxxxxxxxxxxxx]
> Sent: Thursday, March 31, 2005 3:08 PM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: Removing unused pad rings on inner layers
> DURING design...
>
> Julian
>
> So long as there is a pad defined the size of the drill then the
> clearance
> will be as if drill to copper. Even works without any pad, or at least
> used
> to. One trick for no pad power pins is to make sure there is a spacing
> rule
> for the power, give it the priority over everything else and also give
> it
> your desired drill to copper.
>
>
> Best Regards
>
> David Greig
> ______________________________
> GigaDyne Ltd
> Buchan House
> Carnegie Campus
> Dunfermline KY11 8PL
> United Kingdom
> t: +44 (0)1383 624 975
> http://www.gigadyne.co.uk
> ______________________________
>
> -----Original Message-----
> From: MAILER-DAEMON@xxxxxxxxxxxxx [mailto:MAILER-DAEMON@xxxxxxxxxxxxx]
> Sent: 2005-March-31 20:26
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: Removing unused pad rings on inner layers
> DURING
> design...
>
>
> David,
>
> So you are saying that the padstack should be using "drill to copper" by
> default (no pads); If there is a connection on a particular inner layer,
> a
> pre defined pad size should be used Instead. I like that.
>
> Thanks,
> Julian
>
> -----Original Message-----
> From: David Greig [mailto:david@xxxxxxxxxxxxxx]
> Sent: Thursday, March 31, 2005 11:14 AM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: Removing unused pad rings on inner layers
> DURING
> design...
>
> Hi Austin,
>
> There does not seem to be any way of doing this. I too prefer to err
> towards
> drill to copper clearances rather than have unused pads.
> Certainly for power planes under area array devices this significantly
> reduces the colander effect, and so long as one is aware of CAF this is
> preferable.
> Designing without non-functional pads is highly preferable for the very
> reason that some 3D solver translators still include them even if the
> padstack is optional.
> If only normal routing would choose an appropriate padstack in the same
> way
> as blind/buried. Padstack editor unfortunately does not allow a
> blind/buried
> definition if both top and bottom pads are defined. There is no easy
> workaround.
>
> If Cadence are listening, please remove some of the formal hard coded
> rules
> and allow drilled vias with selective internal pads to be used in the
> same
> way as blind/buried.
> A drill to copper clearance rule set would also be nice...
>
>
> Best Regards
>
> David Greig
> ______________________________
> GigaDyne Ltd
> Buchan House
> Carnegie Campus
> Dunfermline KY11 8PL
> United Kingdom
> t: +44 (0)1383 624 975
> http://www.gigadyne.co.uk
> ______________________________
>
> -----Original Message-----
> From: Austin Franklin [mailto:austin@xxxxxxxxxxxx]
> Sent: 2005-March-31 18:29
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Removing unused pad rings on inner layers DURING
> design...
>
> Hi,
>
> Is there a way to not have inner layer pad rings show up unless a trace
> is
> connected to it on that specific layer? I know that the pad rings can
> be
> removed by the fabricator, but I want to remove them during design to
> allow
> for more clearance for routing between vias. How I've handled this in
> another tool is to set-up custom padstacks that have pad rings only on
> the
> two outer layers, and the one internal layer. It worked fine, but
> obviously
> required more work when picking vias.
>
> Regards,
>
> Austin
>
>
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