[PCB_FORUM] Re: Removing unused pad rings on inner layers DURING design...
- From: chris.ball@xxxxxxxxx
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Fri, 1 Apr 2005 12:03:20 -0400
I have to admit I don't fully have my brain around the mfg.tol. subject. I
thought it was to allow for layer to layer mis-registration, drill
mis-registration/perpendicularity, and maybe some things I'm not
considering besides hole tolerance and conductor-width tolerance.
....So, say you have a 301V transient potential between two nodes and so
set your constraints to space these at 10 mils on the internal layers. Are
you really OK if mfg.tol is not added to drill size for the internal 'pad'?
Doesn't sound like it applies to Austin's application; just theoretical
friday crap, I guess....
-Chris
"Musetti, Carl"
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[PCB_FORUM] Re: Removing unused
pad rings on inner
layers DURING design...
04/01/2005 10:38 AM
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icu-pcb-forum
Yes Chris that is exactly what I am saying but I still would advise
completely ignoring manufacturing tolerance. as the is a tolerance on where
the drill head actually hits the board vs. specified XY coordinate in the
drill file. I believe this is referred to as drill wandering. Another thing
to be aware of is that many drill machines are only calibrated to a mil, so
you can specify coordinates in sub mil values in your drill file but if the
drill machine is only calibrated to a mil then those sub mil values will be
truncated and the true drill position could be as much as a half mil
different than the design. For this reason I wish allegro had a via grid
sometimes! If you use IPC standard manufacturing tolerance you can probably
take the laminate anywhere that can build to IPC standards, which is pretty
much most of them. I would check with the fab vendor 1st. Many shops can do
better than the IPC standard tolerances which will give you more space but
the down side of that i
s you may be lock into that vendor.
-----Original Message-----
From: chris.ball@xxxxxxxxx [mailto:chris.ball@xxxxxxxxx]
Sent: Friday, April 01, 2005 10:10 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Removing unused pad rings on inner layers
DURING design...
Both good points.
Carl is stressing the fact that DRILL size is not the same as FINISHED HOLE
SIZE (after plating). For internal layers, you need to focus on drill size.
If you specify a 10mil finished hole size on the via, then make sure your
internal pad is upsized to the actual drilled hole.
You might get by without worrying about adding std. mfg. tol. Depends. If
you have a min clearance for higher voltage potential, then you'd want to
add it in. If your electrical spacing requirements can live with min
spacing minus mfg.tol., then you're OK (I think).
-Chris
"Austin Franklin"
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[PCB_FORUM] Re: Removing unused
pad rings on
inner layers DURING design...
04/01/2005 09:48 AM
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icu-pcb-forum
Hi Carl,
> I'm sure most of you are aware of this but when you talk about
> making a pad size the size of the drill you need to consider that
> pad size as the actual drill bit size not finished drill + the
> standard manufacturing tolerances. Then you would apply that
> minimum clearance to that pad shape.
I think you want to increase the "pad" size larger than the drill size by
that "standard manufacturing tolerance" (for me, that would be 10 mils plus
3 mils) so that you can use the default trace to via clearance. If you
make
the pad the size of the drill, then you have to increase the trace to via
clearance to include this "standard manufacturing tolerance", which would
then apply to every trace to via, not just the ones with the pads
"removed".
I agree, that making a via with no "regular" internal pads, and then
running
a skill script to add the "regular" pads to places where connections were
made is a great idea, and would make this issue really easy to solve.
Regards,
Austin
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