My 2 cents
Carl
-----Original Message-----
From: MAILER-DAEMON@xxxxxxxxxxxxx [mailto:MAILER-DAEMON@xxxxxxxxxxxxx]
Sent: Thursday, March 31, 2005 5:06 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Removing unused pad rings on inner layers
DURING design...
OK, so what if you defined the via "pad" to be the hole size. Then
each via you routed to on a certain layer, where you really wanted a
full size "pad", you could add a circular filled shape at the via site.
It's still manual, but a lot less work than messing with multiple via
padstacks.
And ... I'm guessing that if you were proficient in skill, a program
could be written to add the little circular shapes wherever a via had a
connection made.
-----Original Message-----
From: David Greig [mailto:david@xxxxxxxxxxxxxx]
Sent: Thursday, March 31, 2005 3:08 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Removing unused pad rings on inner layers
DURING design...
Julian
So long as there is a pad defined the size of the drill then the
clearance
will be as if drill to copper. Even works without any pad, or at least
used
to. One trick for no pad power pins is to make sure there is a spacing
rule
for the power, give it the priority over everything else and also give
it
your desired drill to copper.
Best Regards
David Greig
______________________________
GigaDyne Ltd
Buchan House
Carnegie Campus
Dunfermline KY11 8PL
United Kingdom
t: +44 (0)1383 624 975
http://www.gigadyne.co.uk
______________________________
-----Original Message-----
From: MAILER-DAEMON@xxxxxxxxxxxxx [mailto:MAILER-DAEMON@xxxxxxxxxxxxx]
Sent: 2005-March-31 20:26
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Removing unused pad rings on inner layers
DURING
design...
David,
So you are saying that the padstack should be using "drill to copper" by
default (no pads); If there is a connection on a particular inner layer,
a
pre defined pad size should be used Instead. I like that.
Thanks,
Julian
-----Original Message-----
From: David Greig [mailto:david@xxxxxxxxxxxxxx]
Sent: Thursday, March 31, 2005 11:14 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Removing unused pad rings on inner layers
DURING
design...
Hi Austin,
There does not seem to be any way of doing this. I too prefer to err
towards
drill to copper clearances rather than have unused pads.
Certainly for power planes under area array devices this significantly
reduces the colander effect, and so long as one is aware of CAF this is
preferable.
Designing without non-functional pads is highly preferable for the very
reason that some 3D solver translators still include them even if the
padstack is optional.
If only normal routing would choose an appropriate padstack in the same
way
as blind/buried. Padstack editor unfortunately does not allow a
blind/buried
definition if both top and bottom pads are defined. There is no easy
workaround.
If Cadence are listening, please remove some of the formal hard coded
rules
and allow drilled vias with selective internal pads to be used in the
same
way as blind/buried.
A drill to copper clearance rule set would also be nice...
Best Regards
David Greig
______________________________
GigaDyne Ltd
Buchan House
Carnegie Campus
Dunfermline KY11 8PL
United Kingdom
t: +44 (0)1383 624 975
http://www.gigadyne.co.uk
______________________________
-----Original Message-----
From: Austin Franklin [mailto:austin@xxxxxxxxxxxx]
Sent: 2005-March-31 18:29
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Removing unused pad rings on inner layers DURING
design...
Hi,
Is there a way to not have inner layer pad rings show up unless a trace
is
connected to it on that specific layer? I know that the pad rings can
be
removed by the fabricator, but I want to remove them during design to
allow
for more clearance for routing between vias. How I've handled this in
another tool is to set-up custom padstacks that have pad rings only on
the
two outer layers, and the one internal layer. It worked fine, but
obviously
required more work when picking vias.
Regards,
Austin
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