[PCB_FORUM] Re: Removing unused pad rings on inner layers DURING design...
- From: "Austin Franklin" <austin@xxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Fri, 1 Apr 2005 12:14:38 -0500
Hi Chris,
> Both good points.
Thank you.
> Carl is stressing the fact that DRILL size is not the same as
> FINISHED HOLE
> SIZE (after plating).
Absolutely true.
> For internal layers, you need to focus on
> drill size.
Exactly.
> If you specify a 10mil finished hole size on the via, then make sure your
> internal pad is upsized to the actual drilled hole.
I specify 10 mil drill only, not finished hole size.
> You might get by without worrying about adding std. mfg. tol. Depends. If
> you have a min clearance for higher voltage potential, then you'd want to
> add it in. If your electrical spacing requirements can live with min
> spacing minus mfg.tol., then you're OK (I think).
As was pointed out in another post, the oversize is pretty much for other
things, like registration, wobble etc. No voltage issue on the boards I do.
Regards,
Austin
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