[SI-LIST] Re: Tools to Create IBIS Models
- From: "Craig Twardy" <ctwardy@xxxxxxxxxxxxxxxxxx>
- To: swldstn@xxxxxxxxxxxx, tom@xxxxxxxxxxxxx, MikonCons@xxxxxxx,si-list@xxxxxxxxxxxxx
- Date: Tue, 23 Mar 2004 09:10:00 -0500
Steve;
Tools we have found useful for this are Microsoft project manager and test
vehicles.
Build and measure a test vehicle to confirm device performance and models
(spice, ibis, whatever)
This should be done well before top level design is completed, so as to stay
off the critical path.
Typically the simpler the test vehicle the easy and better the measurements
and model correlation.
This also allows process spread verification as Michael Conn mentioned.
Craig
-----Original Message-----
From: Steven M. Waldstein [mailto:swldstn@xxxxxxxxxxxx]
Sent: March 22, 2004 10:07 PM
To: tom@xxxxxxxxxxxxx; MikonCons@xxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Tools to Create IBIS Models
To all,
This is very interesting about creating IBIS models from measured parts but
for us this happens about 6 months too late. Our customers want reliable,
accurate models while we finalizing the top level of our parts and while
they are being fabricated. This way they can have there boards ready and
built when we are ready to provide first customer samples. We always do lab
characterization or parts to validate our silicon design flow but again,
this is just validation. If we can not properly predict the performance of
our IO buffer designs we have failed to meet customer schedules. Also its
interesting that people appear to have some many problems with ESD
structures. We have come to expect that proper modeling, at the HSPICE
level, of our pre-fab layouts, and packages, is done properly. Designing IO
that run at rates of up to 3.125 GHz can't be done without accurate
extraction and package modeling. Also before anyone asks, we do not expect
to create IBIS models for IOs that run at these speeds but we do expect to
accurately model these in HSPICE.
So I'll ask the question again. Does anyone have tools they
can recommend?
Steve
swldstn@xxxxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]On
Behalf Of Tom Dagostino
Sent: Monday, March 22, 2004 1:13 PM
To: MikonCons@xxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Tools to Create IBIS Models
Mike
There are several errors I have seen in SPICE descriptions of I/O buffers.
Missing clamps is just one example. More important are the basic issues
with correlation between the IV curves that SPICE predicts and what we have
actually measured. I have downloaded IBIS models from manufacturer's web
pages. I have compared those IV tables with measurements I have made on
sample ICs with lot date codes near the published dates of those IBIS
models. Sometimes there is good agreement. In many cases I've seen room
temperature, nominal voltage IV measured curves that fall outside the limits
of the Min/Max of the SPICE extraction. Typically the measured curves were
stronger than the max in the SPICE derived model.
There are two ways that Teraspeed Labs has made min/typ/max IBIS models from
measurement. One is taking a sample in characterizing it over temperature
and voltage and stating in the model that the min and max represent voltage
and temperature only. Over the years we have seen many die from many
different lots of the same manufacturing lots. We have noticed that there
is very good consistency over time of the performance of the I/O buffers
unless there was an obvious process change. Modern IC process tend to be
very consistent. I've also had IC vendors or their fabless customers tell
me that there is not much variation between lots.
The other way we have made Min/typ/max models is to get process skew ICs. We
measure different process corners to get the different IBIS corners. This is
easy to get corner lots for a CMOS process if they want to spend the time
but difficult for the bipolar processes.
Tom Dagostino
Teraspeed Consulting Group LLC
Device Modeling Division
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
tom@xxxxxxxxxxxxx <mailto:tom@xxxxxxxxxxxxx>
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
http://www.teraspeed.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]On
Behalf Of MikonCons@xxxxxxx
Sent: Monday, March 22, 2004 9:34 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Tools to Create IBIS Models
In a message dated 3/21/2004 10:37:43 AM Pacific Standard Time,
scott@xxxxxxxxxxxxx writes: If a Spice model is created with impropper
assumptions or by leaving out important elements of the circuits (like ESD
structures) it will not be very accurate. IBIS models, on the other hand,
can be created directly from measurement and are as accurate as the
measurements we take. Teraspeed Labs has measurement based IBIS models that
accurately reflect the device operation. With full process corner silicon,
we have developed models which are more accurate than the original Spice
models (as reported by our customers, the IC vendors themselves.)
**************
Scott:
You are right on target re: ESD structures. I have found the clamping
networks (or lack of inclusion of their affects in the IBIS models) are a
very common source of error. It is these very networks that contribute the
maximum variation of driver and receiver output/input capacitance as a
function of signal voltage, which in turn alter the rising and falling edges
of the signals. That is one of the key elements in my paper.
Some of your comments raised my eyebrows a bit..."IBIS models, on the other
hand, can be created directly from measurement and are as accurate as the
measurements we take. Teraspeed Labs has measurement based IBIS models that
accurately reflect the device operation....and..." If you want to know if
your IBIS model is accurate, do the same, or create it directly from
measurements, as we do."
I have seen and appreciated your modeling work (which IMHO was reflected in
one of the best papers at DesignCon 2004), but I am puzzled as to how one
would extrapolate lab measurements to models that correctly reflect/predict
the corners of silicon processes. I would think that any reasonable number
of measurements on real devices would still fall within the one-sigma range
of performance. I have used model parameter extrapolations (based on
historically documented process tolerances supplied by cooperative silicon
vendors) for very critical modeling applications, but there is always some
inherent error risk in those extrapolations. I also found that my clients
were initially reluctant to add compensating design margins (with its
attendant cost impact) when such extrapolations were not confirmed by room
ambient lab tests. (But they ultimately agreed because of the criticality of
their application.)
Respectfully,
Mike
Michael L. Conn
Owner/Principal Consultant
Mikon Consulting
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