[SI-LIST] Timing analysis
- From: pom gud <pomgud@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 10 Feb 2004 05:39:45 -0800 (PST)
Hello,
I have doubt about timing waveforms of memory devices
like SRAM, Flash etc.
case I
In data sheets it is mentioned that data will be
available after 55 ns (min)of assertion of chip select
signal and after 25 ns(min) of assertion of Output
enable signal.
My question is if i asserted chip select and output
enable simultaneously then what is the min time after
which data will be available?
Case II
In data sheets it is mentioned that data will be
available after 55 ns (max and min value is not
mentioned)of assertion of chip select signal and after
25 ns(max and min value is not mentioned) of
assertion of Output enable signal.
My question is if i asserted chip select and output
enable simultaneously then what is the min time after
which data will be available?
Waiting for valuable inputs.....
Thanks in advance
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