[SI-LIST] Re: Timing analysis
- From: "Edi Fraiman" <Edi.Fraiman@xxxxxxxxxxxxx>
- To: <erdinih@xxxxxxxxx>, <mhar_be@xxxxxxxxx>
- Date: Sun, 18 Dec 2005 13:53:51 +0200
Hi,
The article by Bob Kirstein cover only the common-clock timing (single
clock is shared by driving receiving agents on a bus).
You could find another technique called source synchronous
timing (the strobe or clock is sent from the driver chip instead of a
separate clock source). This technique described in "A Handbook of
Interconnect Theory and Design Practices", Stephen H. Hall, Garrett W.
Hall, James A. McCall.
Edi
=20
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Ihsan Erdin
> Sent: Thursday, December 15, 2005 8:00 PM
> To: mhar_be@xxxxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Timing analysis
>=20
> Hi Marsha,
> The article by Bob Kirstein answers your questions. Follow the link
> http://www.edn.com/article/CA236412.html
>=20
> Ihsan
>=20
> On 12/15/05, m har <mhar_be@xxxxxxxxx> wrote:
> >
> > Hi all,
> >
> > Can you please guide me in performing post layout timing analysis.
> > How to calculate hold time, setup time , setup margin, hold margin
from
> > the simulated wave form. (what is the formulas used).
> >
> > Thanks and Regards
> > marisha
> >
> > ---------------------------------
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