[SI-LIST] Re: Timing analysis
- From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
- To: "pratap simha" <pratapasimha@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 7 Jan 2010 18:59:58 -0000
hello.
check my calculator:
http://www.buenos.extra.hu/iromanyok/PCB_Timing_analysis.xls
if you have any comment, you can send me an email.
i have tried to cover all topologies, timing verification and also trace
length calculation.
regards,
istvan nagy
concurrent technologies plc.
----- Original Message -----
From: "pratap simha" <pratapasimha@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>; <pratapasimha@xxxxxxxxx>
Sent: Thursday, January 07, 2010 1:57 PM
Subject: [SI-LIST] Timing analysis
> Hello Experts,
> Can anyone please send me the standard excel spreadsheet template for
> timing
> analysis for different interfaces, i.e, for calculating Setup and hold
> time
> margins, using equations.
> I'm verifying timing margins for different interfaces , common clock,
> source
> synchronous (also double data rate), and Asynchronous schemes using
> Hyperlynx tool.
>
> Thanking you in advance,
> Pratapsimha
>
>
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