[SI-LIST] Re: Timing analysis
- From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 07 Jan 2010 16:49:01 +0100
Hi,
My understanding is, that Pratapsimha is not asking for timing analysis
with e. g. Synapticad, but for a Timing budget calculation based on an
analog signal integrity simulation, correct ?
I thought Hpyerlynx would already provide some Timing verification
(Timing budget calculation) tool for different interfaces ?!?
We created our own in excel for Memory interfaces (DDR2/DDR3). But there
is really a lot of work in this template, as it takes automatically the
derating based on slew rate into account.
So I have to admit this was to much work to share it for free ...
regards
Hermann
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Veilchenstrasse 1
94554 Moos
Tel.: +49 (0)9938 / 902 083
Mobile: +49 (0)176 / 787 787 77
Fax: +49 (0)3212 / 121 9008
schrieb Zelno, John:
> Trying to do a timing analysis with a spreadsheet is quite complicated,
> as you need to look at numerous relationships between each of the
> signals in an interface. You'd be much better off using a timing
> analysis tool. We've used SynaptiCAD's tools (http://www.syncad.com -
> Timing Diagramer Pro, Waveformer Pro, Datasheet Pro) with great success.
> You can also consider TimingDesigner (http://www.timingdesigner.com -
> formerly Chronology's tool, now with EMA Design Automation).
>
> -John Zelno
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of pratap simha
> Sent: Thursday, January 07, 2010 5:58 AM
> To: si-list@xxxxxxxxxxxxx; pratapasimha@xxxxxxxxx
> Subject: [SI-LIST] Timing analysis
>
> Hello Experts,
> Can anyone please send me the standard excel spreadsheet template for
> timing analysis for different interfaces, i.e, for calculating Setup and
> hold time margins, using equations.
> I'm verifying timing margins for different interfaces , common clock,
> source synchronous (also double data rate), and Asynchronous schemes
> using Hyperlynx tool.
>
> Thanking you in advance,
> Pratapsimha
>
>
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