[SI-LIST] Re: Timing analysis
- From: pratap simha <pratapasimha@xxxxxxxxx>
- To: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Sat, 9 Jan 2010 17:26:52 +0530
Thank you everyone, also thank you istvan nagy for sharing the template.
I've created an excel template for verifying timing margins , setup and hold
for ethernet MAC RGMII interface,( Source Synchronous)
where data TD[0:3] is presented at both rising and falling edges of the
clock 125mHz. here is the link for the timing diagram.
Please correct me if i'm wrong!
Tsu (margin) = clock_period /2 - Hyperlynx_max_data_delay - T su(min) + clk
to i/p device delay
T h (margin) = clock_period /2 - T hold + Hyperlynx_min_data_delay - clk to
i/p device delay
clk to i/p device delay is gives us pcb trace delay
0.17 " per ns x length of clock trace.
http://docs.google.com/Doc?docid=0AeZ_ASQzzVXnZGY4cHYyeHhfNGNxODZjbmd6&hl=en
also,
skew1: Data to o/p skew at driver : -500(min) 0 (typ) & 500(max)
skew2: Data to i/p skew at reciever: 1.0 (min) & 2.8 (max)
Thanks and Regards
pratap
http://docs.google.com/Doc?docid=0AeZ_ASQzzVXnZGY4cHYyeHhfMGcyZGZyMmY5&hl=en
2010/1/8 Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
> HI Istvan,
>
> nice tool!!
> Thanks for sharing this!
>
> I only checked the Post layout source Sync Sheet vs a Memory based TB,
> and would like to make short comments (maybe you are going to implement
> it in your free time ;-) ):
> For a source sync FSB TB this looks a bit different again.
>
> Memory setup and hold times are defined at AC/DC levels (since DDR2).
> This can be re-calculated to Vref using the risetime.
> Basically both can be used, one just need to take care to take
> consistent values for ISI/X-talk jitter and memory Setup/Hold times.
>
> One thing we are adding since DDR3 times is a package double count: We
> are doing simulations from pad to pad, but the datasheet values for
> output timings are defined at the ball.
> Therefore package e. g. X-talk is taken twice into account (if you have
> a realistic package model that includes X-talk). In this case we did a
> simulation with the package only driving into ideal termination and
> subtracted package introduced ISI. This is of course also not completely
> correct, but a good 1st order approximation of the effect ...
>
> Thanks again and best Regards
>
> Hermann
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.EyeKnowHow.de
> Hermann.Ruckerbauer@xxxxxxxxxxxxx
> Veilchenstrasse 1
> 94554 Moos
> Tel.: +49 (0)9938 / 902 083
> Mobile: +49 (0)176 / 787 787 77
> Fax: +49 (0)3212 / 121 9008
>
>
> schrieb Istvan Nagy:
> > hello.
> >
> > check my calculator:
> > http://www.buenos.extra.hu/iromanyok/PCB_Timing_analysis.xls
> > if you have any comment, you can send me an email.
> > i have tried to cover all topologies, timing verification and also trace
> > length calculation.
> >
> > regards,
> > istvan nagy
> > concurrent technologies plc.
> >
> >
> > ----- Original Message -----
> > From: "pratap simha" <pratapasimha@xxxxxxxxx>
> > To: <si-list@xxxxxxxxxxxxx>; <pratapasimha@xxxxxxxxx>
> > Sent: Thursday, January 07, 2010 1:57 PM
> > Subject: [SI-LIST] Timing analysis
> >
> >
> >
> >> Hello Experts,
> >> Can anyone please send me the standard excel spreadsheet template for
> >> timing
> >> analysis for different interfaces, i.e, for calculating Setup and hold
> >> time
> >> margins, using equations.
> >> I'm verifying timing margins for different interfaces , common clock,
> >> source
> >> synchronous (also double data rate), and Asynchronous schemes using
> >> Hyperlynx tool.
> >>
> >> Thanking you in advance,
> >> Pratapsimha
> >>
> >>
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