[SI-LIST] Re: Timing analysis
- From: Dan Smith <Dan.Smith@xxxxxxxxx>
- To: pratap simha <pratapasimha@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 7 Jan 2010 08:37:14 -0800
Pratapsimha,
I do have some templates (DDRs, source synchronous, buffered clock models,
etc.) but as many have eluded to it can be time consuming and gets complicated
if real (but when all said and done its just algebra). I wouldn't be able to
send it via this email anyway. However, I would recommend that all board
engineers go through this exercise of creating a template (e.g.. for DDR) at
least once as the insight gained is fairly large. In my experience, many
designers use the off the shelf tools (and they are good) but lack the
understanding of what is really happening and what rules are really necessary
to put in the design to guarantee margins. And, I have seen (on more than one
occasion) a lack of this understanding by the person representing the vendor
that is demonstrating the tool.
We all look for expedient ways for our designs but I believe this investment is
well worth the effort and will save you time when used over multiple designs.
(and you get the understanding to "sniff" out when somebody is feeding you a
line of bull).
Regards,
Dan
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of pratap simha
Sent: Thursday, January 07, 2010 5:58 AM
To: si-list@xxxxxxxxxxxxx; pratapasimha@xxxxxxxxx
Subject: [SI-LIST] Timing analysis
Hello Experts,
Can anyone please send me the standard excel spreadsheet template for timing
analysis for different interfaces, i.e, for calculating Setup and hold time
margins, using equations.
I'm verifying timing margins for different interfaces , common clock, source
synchronous (also double data rate), and Asynchronous schemes using
Hyperlynx tool.
Thanking you in advance,
Pratapsimha
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