[SI-LIST] Re: Timing analysis
- From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
- To: "Jennifer Maharani" <jennifer.maharani@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 28 May 2009 18:12:56 +0100
hi
i think we deal with timing in 2 a littlebit different aspects :
-on-board interface and interconnect timing. taking every chip as a black
box. specifying PCB layout length and matching constraints, validating the
designs.
-on chip logic and interconnect timing, and IO timing seen from the chip.
Mostly for VLSI/ASIC/FPGA-based on-chip logic design, but also to understand
board-level timing too.
if you think about it, they are the same thing, but at a littlebit different
starting points.
Greg Edlunds book is trying to talk about the first one, but I think lots of
things are missing from that. so, i would suggest to check also the jedec
79B, 79C, 21C standards, and search for appnotes, from Texas instruments,
Altera, Micron, Cadence. But for start, Gregs book is quiet good.
About the second one, i would suggest this one: (I just started reading it
few days ago. its a brand new book)
http://www.amazon.com/Static-Timing-Analysis-Nanometer-Designs/dp/0387938192/ref=sr_1_1?ie=UTF8&s=books&qid=1241797932&sr=8-1
regards,
Istvan Nagy,
CCT, UK
----- Original Message -----
From: "Jennifer Maharani" <jennifer.maharani@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Thursday, May 28, 2009 7:32 AM
Subject: [SI-LIST] Timing analysis
> Dear experts,
>
> What is timing analysis?
> What do I need to compare e.g. data, strobe ?
> Is there any book or article explaining the procedure in detail?
>
> Many thanks,
> Jenni
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