[SI-LIST] Re: Buried uStrip question
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "Mitch S. Morey" <cadpro2k@xxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Tue, 10 Feb 2004 08:53:45 -0800
Mitch,
You are right, there is a lot of confusion on this topic.
My first choice is to use layer 2 and n-1 for controlled impedance traces.
The reason is that the impedance is more uniform on these layers than it is
on the surface. I do use layer 1 and n on PCBs where cost is a big issue.
When I use these layers, I allow more of the noise tolerance budget for
impedance variations. I don't worry all that much about the effect of
solder mask, because the impedance variations due to nonuniform plating on
the outer layer traces is much larger.
Those who agonize over the effect of soldermask would do well to study the
effects of nonuniform plating on outer layers on impedance. It is a much
bigger variable.
As to EMI on outer layers as opposed to stripline layers or buried
microstrip line layers, I have a test PCB with the same length traces on
all three types of layers that anyone who wants to make tests to compare
each is welcome to do so.
I will make the same tests in the near future and publish them.
Hope this helps.
Lee
> [Original Message]
> From: Mitch S. Morey <cadpro2k@xxxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Cc: <leeritchey@xxxxxxxxxxxxx>
> Date: 2/9/2004 2:38:13 PM
> Subject: Re: [SI-LIST] Re: Buried uStrip question
>
> Hi Lee,
>
> Like a lot of people, I'm sure, what approach do you employ? I still can't
> seem to read between the lines:
>
> 1) Routing allowed on the outer layers, with soldermask covering
> 2) Non-critical routing allowed on outers
> 3) No routing allowed on the outer layers
> 4) Routing allowed, but having a "pad cap" covering
> 5) Other
> 6) If other, please explain.
>
> Many thanks.
>
> Mitch
>
> >
> > The normal method for constructing multilayer PCBs is to build inner
> > layers
> > in pairs on opposite sides of pieces of laminate. These are then
> > separated
> > by pieces of prepreg. The top and bottom layers are formed by pieces of
> > copper foil that is separated from the first buried layer with prepreg.
> > This is commonly called "foil" lamination. It is the least expensive
way
> > to manufacture multilayer PCBs.
> >
> > Lee
> >
> >
> >> [Original Message]
> >> From: steve weir <weirsp@xxxxxxxxxx>
> >> To: Grasso, Charles <Charles.Grasso@xxxxxxxxxxxx>; MikonCons@xxxxxxx
> > <MikonCons@xxxxxxx>; leeritchey@xxxxxxxxxxxxx <leeritchey@xxxxxxxxxxxxx>
> >> Cc: si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>
> >> Date: 2/2/2004 8:17:46 PM
> >> Subject: Re: Buried uStrip question
> >>
> >> Charles, no as I have read him, Lee promotes putting prepreg w/o foil
on
> >> the outside.
> >>
> >> Regards,
> >>
> >>
> >> Steve.
> >> At 09:01 AM 2/2/2004 -0700, Grasso, Charles wrote:
> >> >Steve, AFAIK, a buried ustrip is a ustrip with soldermask.
> >> >Is there another definition? I am unsure as to why one
> >> >would advocate a buried ustrip over a "true" surface ustrip
> >> >when (for typical boards) only buried ustrips prevail.
> >> >
> >> >Best Regards
> >> >Charles Grasso
> >> >Senior Compliance Engineer
> >> >Echostar Communications Corp.
> >> >Tel: 303-706-5467
> >> >Fax: 303-799-6222
> >> >Cell: 303-204-2974
> >> >Email: charles.grasso@xxxxxxxxxxxx;
> >> >Email Alternate: chasgrasso@xxxxxxxx
> >> >
> >> >
> >> >-----Original Message-----
> >> >From: steve weir [mailto:weirsp@xxxxxxxxxx]
> >> >Sent: Monday, February 02, 2004 5:44 AM
> >> >To: MikonCons@xxxxxxx; leeritchey@xxxxxxxxxxxxx
> >> >Cc: si-list@xxxxxxxxxxxxx
> >> >Subject: [SI-LIST] Re: Traces don't cause EMI - really?
> >> >
> >> >Mike, I think the issue is worth reviewing under current
> >> >circumstances. Some understandings have improved greatly with regard
> >> to
> >> >antenna design and/or detuning, and geometries have definitely changed
> > for
> >> >the better. Lee advocates a buried microstrip for the outermost
> >> routing
> >> >layer. That captures the vast majority of the field in the
dielectric.
> >> >
> >> >It's been a long time since I read those old papers going back to the
> >> mid
> >> >eighties when stripline started getting promoted for EMI. But I am
> >> >confident that we will find all of those studies compared surface
> >> >microstrip to stripline. It would be interesting to repeat your 50
ohm
> >> >tests with this "buried microstrip" versus a true surface microstrip
> >> for
> >> >EMI.
> >> >
> >> >Regards,
> >> >
> >> >Steve
> >> >
> >> >At 03:30 PM 2/1/2004 -0500, MikonCons@xxxxxxx wrote:
> >> > >In a message dated 2/1/2004 9:35:10 AM Pacific Standard Time,
> >> > >leeritchey@xxxxxxxxxxxxx writes:
> >> > >Wow! This topic keeps coming up. Wasn't so long ago that we had a
> > very
> >> > >long exchange where proponents of this notion provided the research
> > papers
> >> > >that supported it. I got copies of all of them and looked for some
> >> > >objective measurement of the EMI caused by a trace routed on an
outer
> > layer
> >> > >over a plane and then moved below the plane.
> >> > >None of the papers did such an experiment in a way that could be
used
> > to
> >> > >bet money on. I pointed out that the real source of EMI from a PCB
> > were
> >> > >the lead frames of components that stick up from the PCB. While at
> > Maxtor,
> >> > >we had this very problem with disc drives. We fixed the problem by
> >> > >changing lead frames from PLCCs to QFPs- packages that don't stick
up
> > very
> >> > >far from the PCB. If you want to see this in action, go to Frys or
> >> any
> >> > >place else that sells stand alone disc drives and look at how the
> >> PCBs
> > are
> >> > >designed. All of the signal traces are on outside layers and all of
> > the
> >> > >disc drives comply with CISPRB B.
> >> > >
> >> > >We used a pedicel of equipment that allowed the PCB to be laid on it
> > and
> >> > >then scanned to provide a 2D picture of where emission were coming
> > from. I
> >> > >cannot remember the name of the tool, but it had a table with a grid
> > on it
> >> > >on which the PCB was mounted. The output looked a lot like what one
> > gets
> >> > >from a thermal mapping tool showing places with higher emissions.
> >> The
> >> > >sources of EMI were very clear- the IC lead frames.
> >> > >Thanks, Lee, for including me on your distribution.
> >> > >
> >> > >I absolutely agree that high-speed boards can be designed with many
> > traces
> >> >on
> >> > >the PCB surfaces IF there is a high integrity enclosure.
> >> > >
> >> > >The tool you mentioned was likely of thick, planar construction with
> > many
> >> > >separate pickup coils in a grid. I have seen several test labs with
> > this
> >> > >tool. As
> >> > >you indicated, the lead frames DO radiate substantially. Assuming
> > buried
> >> >PCB
> >> > >traces, some of this radiation can be cancelled by routing the lead
> >> pad
> >> >back
> >> > >under the package before dropping the via. Aside from that, the tool
> > pickup
> >> > >coils detect near fields; hence, the lead frames (because of their
> > closer
> >> > >proximity to the pickup coils) indicate a disproportionately high
> >> field
> >> >level
> >> > >relative to any PCB surface (microstrip) traces. The field strength
> >> is
> >> > >comprised of
> >> > >first-order, second-order, and third-order rolloff terms. Therefore,
> > the
> >> > >field
> >> > >signature would show much less relative differences (even with very
> > small
> >> > >spacing displacements) because of an exponential rolloff in the
> >> coupled
> >> > >signal;
> >> > >hence, some test results may be misleading. Please be aware that I
am
> > in
> >> > >agreement with you on the benefits of low-profile lead packages. Any
> >> > >disbeliever
> >> > >should measure the fields from a small daughter board connected via
> >> > >standoffs of
> >> > >1/4 to 3/8 inch length, as the results will scare you.
> >> > >
> >> > >Re: your statement, "None of the papers did such an experiment in a
> >> way
> >> >that
> >> > >could be used to bet money on."
> >> > >
> >> > >As (many months) before, I disagree. I demonstrated the relative
> > radiation
> >> > >and crosstalk performance of microstrip (50 & 100 Ohm lines),
guarded
> >> > >microstrip
> >> > >(50 Ohms), stripline (50 Ohms), and guarded stripline (50 Ohms) as
> > part of
> >> > >the (now ancient) Hewlett-Packard High-Speed Digital Design Seminar
> > Series
> >> > >(that
> >> > >included such respected pros as Ed Sayre, Eric Bogatin, and Henri
> > Merkelo).
> >> > >The results were clear that either containment (via an enclosure) or
> > the
> >> > >use of
> >> > >stripline was needed for FCC or CISPR Class B compliance. The data
> >> and
> >> > >knowledge gained from these findings led to the redesign of scores
> > (yes,
> >> > >hundreds)
> >> > >of EMI-deficient PCBs over the following decade that achieved a
> > typical 20
> >> >dB
> >> > >(some as high as 40 dB) reductions in radiated emissions. No one has
> > yet to
> >> > >find that the HP spectrum analyzers, HP near-field probes, EMCO
> > (far-field)
> >> > >antennas and near-field probes that I used (and still use) were
> > technically
> >> > >deficient in any way. Additionally, my software predictions support
> >> the
> >> > >empirical
> >> > >test data as well.
> >> > >
> >> > >My concern (and the only reason I'm sending these comments) is that
> > less
> >> > >experienced designers than yourself will think surface traces are
"no
> >> > >problem" and
> >> > >NOT employ the many other routing techniques that you and I have
> > learned
> >> >over
> >> > >the years to be beneficial (or mandatory) for a successful design.
> >> >Obviously,
> >> > >non-enclosed/shielded designs will suffer most from this oversight.
> >> > >
> >> > >Good engineering to all,
> >> > >
> >> > >Mike
> >> > >
> >> > >Michael L. Conn
> >> > >Owner/Principal Consultant
> >> > >Mikon Consulting
>
>
>
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