[SI-LIST] Re: Questions on Reference Planes for DDR3 signals
- From: Vinu Arumugham <vinu@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 27 Jun 2012 13:03:14 -0700
Scott,
For a signal going from one Vddq/Vss cavity to another, you only need a
Vddq via and a Vss via. A capacitor is not needed.
Thanks,
Vinu
On 06/27/2012 12:36 PM, Scott McMorrow wrote:
> That would be quite correct, Vinu. You now understand. In a Vss/Vcc
> referenced stripline, there is no effective way to stitch the planes.
> In a Vss/Vss reference stripline there is. In one we can stitch with
> vias. In the other, we gotta go through caps. For a DDR signal
> switching in the vicinity of 1 GHz, the ain't no bypass cap that can
> effectively help with Vss/Vcc referencing. Cavity injection occurs, is
> not suppressed, and tends to rattle around, resonate, and cause worst
> SSO than just inductive bounce. Steve and I showed this in our
> DesignCon paper from several years ago.
>
>
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