[SI-LIST] Re: Questions on Reference Planes for DDR3 signals
- From: "Cheng, Chris" <chris.cheng@xxxxxx>
- To: "weirsi@xxxxxxxxxx" <weirsi@xxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 25 Jun 2012 21:15:55 +0000
Steve,
The way I see single reference works.
Even for a push pull driver, you can pick a reference, I usually pick ground
and make sure the signals reference it along the path. From package planes to
PCB reference plane.
In the case of asymmetric stripline, the reference plane closest to the signal
is the main reference plane.
The other reference plane can have its image current return through the main
reference plane through the plane capacitance and the reference plane switching
vias whenever the signals transition through the reference planes.
The key assumption for this to work is in most high speed I/O at the driver and
terminator/receiver there are on die decoupling caps for the image currents to
switch from ground to power at terminator (for high to low transitions) or
driver (for low to high transitions).
One observation I had with actual measurements of SSO induced "crosstalk" is
they tend to saturate relatively quickly with fast edges such as DDR3 in a
package. You don't need to switch the entire 108 bits of DDR3 to get the
saturated effects on the victim line. Simply the nearest four or five neighbors
will get you close enough if you have a well design package that spread the
power/ground pins evenly. That suggest a TDT experiment on each aggressors to
the victim and mathematically add the noise assuming linear and superposition
works.
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Company
+1 510 413 5977 / Tel
chris.cheng@xxxxxx / Email
4209 Technology Dr
Fremont, CA 94538
USA
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of steve weir
Sent: Monday, June 25, 2012 10:27 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Questions on Reference Planes for DDR3 signals
On 6/25/2012 10:02 AM, Vinu Arumugham wrote:
> Steve,
>
> One can view it as two t-lines - signal/Vdd and signal/Vss - both with
> the same characteristic impedance and both terminated at their
> characteristic impedance - say 100 ohm.
Yes, and each of these lines couples into the driver through the package
inductance. The inductance of the Vss network is lumped as Lvss, and
the inductance of the Vdd network as Lvdd
> For a low-high transition, the
> pull-up structure discharges the signal/Vdd t-line and charges the
> signal/Vss t-line with ~10mA current drawn from the supply.
No, a low to high transition imposes di/dt of the same polarity into
both structures. The signal line is going high: It is drawing positive
convention current through the die PDN and back to the PCB PDN through
both Lvdd and Lvss.
> For a
> high-low transition, the the pull-down structure discharges the
> signal/Vss t-line and the same 10mA from the supply charges the
> signal/Vdd t-line. A constant current from the supply is steered to
> charge the signal/Vss or signal/Vdd t-line. Since there is no switched
> current, di/dt is 0.
No, externally current the switched current is divided in two. It is
still switched. All you need to see this is to draw a black box around
the IC. What the signal line does is complemented by the PDN lines. In
order to cancel so that there is net zero current in the PDN
attachments, you have to reduce the net signal current to zero, such as
trivially with differential or less trivially with an Nb(N+M)q coding
scheme.
>
> Power noise would be limited to crowbar current or a gap in conduction
> between pull-up/pull-down structures. For high performance buffer
> designs, this should already be small.
>
> In the case of a Vss only referenced t-line, the power supply current
> switches between 0-20mA resulting in SSN.
>
> The bus needs to be unidirectional to take full advantage of
> symmetrically referenced signaling.
>
> Thanks,
> Vinu
>
>
> On 06/22/2012 10:05 PM, steve weir wrote:
>> Vinu, a completely balanced transmission path can theoretically divide
>> SSO in half. It does not cancel it. Let us suppose that we have a
>> completely balanced transmission path using a symmetrical stripline all
>> the way back to the die launch. For a given di/dt * N bits
>> transitioning from low to high, relative to BOTH planes the di/dt is
>> positive. If the interconnect is completely symmetrical then we have
>> half the total inductance and half the SSO amplitude. We do not cancel
>> the SSO. The only way to cancel SSO is to code such that the summation
>> of transitions multiplied by polarity equals zero.
>>
>> Steve.
>>
>> On 6/22/2012 10:08 AM, Vinu Arumugham wrote:
>>> Steve,
>>>
>>> A network DRAM package we looked at had signal lines referenced to both
>>> Vddq and Vss. It also had a pinout where the data pins were interspersed
>>> with Vddq and Vss.
>>>
>>> If the DDR3 DRAM package routing is symmetrically referenced to
>>> Vddq/Vss, it enables construction of a signal path that is symmetrically
>>> referenced end-to-end (non-DIMM applications). Along with the fact that
>>> data lines are thevenin terminated to Vddq/Vss, it creates a special
>>> signaling configuration where theoretically SSO would be zero.
>>>
>>> Thanks,
>>> Vinu
>>>
>>> On 06/21/2012 09:23 PM, steve weir wrote:
>>>> Vinu this was the practice with the last packages I looked at several
>>>> years ago.
>>>>
>>>> Steve
>>>> On 6/21/2012 9:49 AM, Vinu Arumugham wrote:
>>>>> Steve,
>>>>>
>>>>> Have you verified that memory packages reference data lines only to Vss?
>>>>> The memory pinout suggests that data lines are referenced to both Vss
>>>>> and Vddq.
>>>>>
>>>>> Thanks,
>>>>> Vinu
>>>>>
>>>>> On 06/21/2012 01:39 AM, steve weir wrote:
>>>>>> Hirshtal, this all amounts to reducing signal disturbance.
>>>>>> Unfortunately, this is another case of: "It all depends." The data
>>>>>> signals constitute the higher data rates as well as the greater number
>>>>>> SSOs, so they deserve more care than the A/C signals. However, if you
>>>>>> want reliable operation at speed, reasonable care must be employed with
>>>>>> both. You have a few basic options:
>>>>>>
>>>>>> 1. Follow a proven topology exactly as though your life depends on it.
>>>>>> Pray that the gods of reference designs will reward your dedicated
>>>>>> obedience by blessing your effort.
>>>>>>
>>>>>> 2. Develop and evaluate design rules that are suitable to your
>>>>>> particular situation. Tool sets are available to evaluate different
>>>>>> topologies, such as from Si-Soft. If you don't have the tools, the
>>>>>> budget, or the time, then you can lean on an outside service to do this
>>>>>> for you.
>>>>>>
>>>>>> 3. Try to develop rules ad-hoc without checking and hope that Murphy
>>>>>> does not decide to amuse himself at your expense. The more conservative
>>>>>> the rules you set, the more likely you can save yourself the wrath of
>>>>>> Murphy.
>>>>>>
>>>>>> Slides 14 and 15 of this presentation available on my web-site
>>>>>> illustrate what you face with different routing topologies:
>>>>>> http://www.ipblox.com/pubs/SVCEMC_May_2005/capacitor_placement_public_b.pdf
>>>>>>
>>>>>> A couple of comments: Memory packages and DIMMs reference data lines to
>>>>>> Vss. DIMMs reference A/C to VDDQ. This was done to support low layer
>>>>>> count PCBs. It works. You will avoid introducing extra noise and
>>>>>> cross-talk by extending those references in your channel end to end.
>>>>>> What your memory controllers reference varies. Any reference change you
>>>>>> introduce will inject energy between the the references used. This can
>>>>>> be handled, but requires work and more analysis. And unless the design
>>>>>> is low performance, it usually imposes more cost for equal performance.
>>>>>>
>>>>>> A final note: Always treat clock with the utmost care. Barring some
>>>>>> terrible cost impact a continuous Vss reference is a good way to treat
>>>>>> clocks.
>>>>>>
>>>>>> Steve
>>>>>> On 6/21/2012 1:42 AM, Hirshtal Itzhak wrote:
>>>>>>> Hello all,
>>>>>>> I've been looking at DDR3 layout guides from Micron and from some
>>>>>>> manufacturers of DDR3 controller devices and haven't found a clear
>>>>>>> recommendation for how to deal with the issue of reference planes for
>>>>>>> DDR3 interfaces in a stripline configuration. Also, there are some
>>>>>>> other "reference-plane" issues which I hope someone can clarify.
>>>>>>>
>>>>>>> So here are the questions I haven't found a clear answer for:
>>>>>>>
>>>>>>> (1) Almost all recommendations that I've
>>>>>>> found are to route data-group signals "adjacent to a solid GND Layer".
>>>>>>> Can I, therefore, route them adjacent to both a GND and a Power plane
>>>>>>> in a stripline configuration? Does it matter if the stripline is
>>>>>>> symmetric (relative to the 2 ref planes) or not?
>>>>>>> (2) Almost all recommendations that I've
>>>>>>> found are to route address/command/control signals "adjacent to a solid
>>>>>>> Power or GND Layer". Can I route them adjacent to a Power plane with a
>>>>>>> voltage different than the DDR3-1.5Volt VDD?
>>>>>>> (3) If DDR-VDD is required, can I use another
>>>>>>> solid Power plane as the other plane in stripline configurations
>>>>>>> (provided the 1st plane is VDD)?
>>>>>>> (4) What reference plane is recommended for
>>>>>>> the Clock pair? Micron, for example, doesn't say anything on this
>>>>>>> matter, but some other manufacturers recommend using only a GND plane.
>>>>>>> Is this true, as far as you know?
>>>>>>>
>>>>>>> Thanks in advance for your help!
>>>>>>>
>>>>>>> Itzhak Hirshtal
>>>>>>> Elta Systems
>>>>>>>
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