[SI-LIST] Questions on Reference Planes for DDR3 signals
- From: Hirshtal Itzhak <ihirshtal@xxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 21 Jun 2012 08:42:08 +0000
Hello all,
I've been looking at DDR3 layout guides from Micron and from some manufacturers
of DDR3 controller devices and haven't found a clear recommendation for how to
deal with the issue of reference planes for DDR3 interfaces in a stripline
configuration. Also, there are some other "reference-plane" issues which I hope
someone can clarify.
So here are the questions I haven't found a clear answer for:
(1) Almost all recommendations that I've found are to
route data-group signals "adjacent to a solid GND Layer". Can I, therefore,
route them adjacent to both a GND and a Power plane in a stripline
configuration? Does it matter if the stripline is symmetric (relative to the 2
ref planes) or not?
(2) Almost all recommendations that I've found are to
route address/command/control signals "adjacent to a solid Power or GND Layer".
Can I route them adjacent to a Power plane with a voltage different than the
DDR3-1.5Volt VDD?
(3) If DDR-VDD is required, can I use another solid
Power plane as the other plane in stripline configurations (provided the 1st
plane is VDD)?
(4) What reference plane is recommended for the Clock
pair? Micron, for example, doesn't say anything on this matter, but some other
manufacturers recommend using only a GND plane. Is this true, as far as you
know?
Thanks in advance for your help!
Itzhak Hirshtal
Elta Systems
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