[SI-LIST] Re: Questions on Reference Planes for DDR3 signals
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Ravinder.Ajmani@xxxxxxxx
- Date: Wed, 27 Jun 2012 11:52:47 -0700
They are proportioning constants. The results that one gets with method
2 versus certain variations of method 3 depend highly on geometry of the
cavities and the stitch via pattern.
Best Regards,
Steve.
On 6/27/2012 9:15 AM, Ravinder.Ajmani@xxxxxxxx wrote:
>
> Hi Steve,
>
> This may look like a dumb question, but please tell me what do X and Y
> represent in your note.
>
> Speaking of the 5 rings of Signal Integrity/EMC hell, the only way to
> accomplish #1 is to route all the signals on Top layer, which is
> practically impossible. I generally use #2 in my designs, and it keeps
> EMI under control. I also did some modeling to determine the effect of
> ground vias, and didn't see any noticeable improvement when using #2
> routing strategy.
>
> Thanks.
>
>
> Regards
> Ravinder Ajmani
> HGST, a Western Digital company
> ravinder.ajmani@xxxxxxxx
>
>
>
>
>
>
>
> *steve weir <weirsi@xxxxxxxxxx>*
> Sent by: si-list-bounce@xxxxxxxxxxxxx
>
> 06/27/2012 12:44 AM
> Please respond to
> weirsi@xxxxxxxxxx
>
>
>
> To
> si-list@xxxxxxxxxxxxx
> cc
>
> Subject
> [SI-LIST] Re: Questions on Reference Planes for DDR3 signals
>
>
>
>
>
>
>
>
>
> Liuluping, SSO noise is almost exclusively the result of di/dt through
> common inductance. Minimizing SSO requires that we minimize the product
> of series inductance and di/dt from the die launch through the entire
> channel. If you have X*N Vddq balls and Y*N Vss balls, the ideal
> distribution is X SSO signals referenced to Vddq for every Y SSO signals
> referenced to Vss. Only if X = Y will you get the lowest noise by evenly
> splitting SSO di/dt between PCB Vss and PCB Vddq. In that case you have
> the option of referencing half of the signals to X and half to Y or
> alternately referencing all signals evenly to X and to Y. That gets you
> us out of the package.
>
> Once we are in the PCB, every time that a signal traverses a cavity, ANY
> cavity it excites that cavity. If the cavity has the same DC rail on
> both planes, then we can button down the cavity with stitch vias.
> Otherwise, we have to use bypass capacitors. Barring embedded
> capacitors, the deeper the cavity is in the board, the harder it will be
> for bypass capacitors to be effective due to the large loop inductance
> imposed by the long distance between the cavity and the capacitor
> mounting surface.
>
> So the best strategy is to: a) Avoid exciting ANY cavity, and b) Where
> we excite a cavity minimize what is required to hold the disturbance to
> an acceptable level. a) and b) will take us to the five types of route
> classes, or as I like to say the five rings of EMC/signal integrity hell
> as outlined by authors like Bruce Archambeault:
>
> a) Route against one surface of one plane end to end.
> b) Route against the surfaces of one plane end to end.
> c) Route against multiple planes that are stitched together with vias.
> d) Route against multiple planes that are stitched together with bypass
> capacitors, IE the two voltages of a given rail.
> e) Route against multiple planes that are stitched together with series
> bypass capacitors, IE unrelated voltages.
>
> The problem with strategy #2 is that it begins life at the fourth ring
> of EMC / signal integrity hell. Whereas #1 never gets deeper than the
> third rail. Within the PCB, strategy #2 will never be able to outperform
> strategy #1. Noted EMC and signal integrity specialist and former First
> Lady Nancy Reagan advises: "Just say no to mixed PCB return references."
>
> Steve.
>
> On 6/26/2012 8:45 PM, Liuluping wrote:
> > Hi steve and all:
> > Thank you for your reply; Can we consider that the strategies 2)
> just separate the SSO noise in two rails instead of just one rail,
> > so reduce noise on each rail, but the sum of the noise on the two
> rail will equal to strategies 1)£¿
> > To make things more clear, lets consider a practical design
> case(here I collect some discussion on the SI-List before, thanks to
> all the people):
> > A Controller with 10pcs DDR3@2133Mbps(NOT DIMM), with 160bit DQ ,20
> diff dqs, 80bit address ,20 diff clk and other signals.
> > To simplify analysis,here we assume that the pin map have designed
> that ,as steve suggest, have equal Lvdd and Lvss (at package).
> > The board is 14 layer boards, may have two solutions:
> > *************************************
> > Solution A:
> > The stackup is :
> > TOP
> > GND02
> > ART03
> > GND04
> > ART05
> > GND06
> > PWR07
> > ART08
> > GND09
> > ART10
> > GND11
> > ART12
> > GND13
> > BOTTOM
> >
> > Key notes:
> > 1)All DDR3 signal route in ART03/05/10/12, couple to two GND plane.
> > 2)VDDIO @PWR07, the distance between GND06 and PWR07 is about 3mil.
> > 3)VTT decouple to only GND.
> > 4)CLK VTT is the same with 3£©.
> > 5) Vref decouple to both VDDIO and GND .
> >
> > Advantage: all signal couple to a "clean" GND, VDDIO close couple to
> GND, may be improve the SSO noise decoupling;
> > Disadvantage: Double the SSO noise compare to solution B?
> >
> > *************************************
> > Solution B:
> > The stackup is :
> > TOP
> > GND02
> > ART03
> > VDDIO
> > ART05
> > GND06
> > PWR07
> > ART08
> > GND09
> > ART10
> > VDDIO
> > ART12
> > GND13
> > BOTTOM
> >
> > Key notes:
> > 1)All DDR3 signal route in ART03/05/10/12, couple to BOTH VDDIO and
> GND plane.
> > 2)VDDIO NOT at PWR07.
> > 3)VTT decouple to both VDDIO and GND.
> > 4)CLK with 36ohm floating terminal ,as the DIMM spec, and decouple
> to VDDIO only.
> > 5) Vref decouple to both VDDIO and GND .
> >
> > Advantage: all signal couple to both VDDIO and GND ,may half the SSO
> noise at VDDIO plane?;
> > Disadvantage: 1) Noisy VDDIO will reduce the margin of the signal;
> > 2) VDDIO not close couple to GND, may worse the VDDIO noise?
> > ***************************************
> > I will choose solution A, How about your opinions?
> >
> > Thanks advance,
> >
> > LIU Luping
> >
> > -----ÓʼþÔ¼þ-----
> > ·¢¼þÈË: steve weir [mailto:weirsi@xxxxxxxxxx]
> > ·¢ËÍʱ¼ä: 2012Äê6ÔÂ26ÈÕ 20:10
> > ÊÕ¼þÈË: Liuluping
> > ³ËÍ: si-list@xxxxxxxxxxxxx
> > Ö÷Ìâ: Re: ´ð¸´: Questions on Reference Planes for DDR3 signals
> >
> > There seems to be some confusion going around about the channel on the
> > PCB, and the package launch.
> >
> > 2) can only reduce the SSO in half under a special set of conditions.
> > That's the best it can do.
> >
> > You can view 2) as taking N 50 Ohm lines and converting them to 2N
> > paired 100 Ohm lines, one line for each that references Vss and another
> > that references Vdd. If Lvdd and Lvss between the PCB and die are equal,
> > then the di/dt through Lvdd and Lvss are each half what it would have
> > been with N 50 Ohm lines referencing only Vdd or Vss with the same Lvss
> > or Lvdd. The assumption of equal Lvss and Lvdd is questionable. It
> > relies on a package designer either naively choosing the number of balls
> > for each rail, or planning for this balanced stripline PCB routing.
> >
> > A smart package designer planning for the method 1) would allocate
> > enough Vdd and Vss connections to realize appropriate Lvdd and Lvss for
> > the number of lines that will reference each. So, if a memory controller
> > had 24 A/C that the designer intends should reference PCB Vdd and 128
> > data lines that should reference PCB Vss, then the ball pattern should
> > have a ratio of about 6 Vss for every Vdd. The key thing to remember is
> > that SSO builds across shared impedance. If the shared impedance is very
> > low relative to the di/dt, and there are not resonance problems, then
> > the SSO will be small. A very conservative package would carry one
> > signal return ball for each single ended signal ball.
> >
> > Signals should only make absolutely necessary reference changes.
> > Differential or not, I recommend routing high speed data lines against a
> > contiguous Vss reference.
> >
> > Steve
> > On 6/26/2012 3:19 AM, Liuluping wrote:
> >> Hi Steve:
> >> Thank you for your quickly reply, your explain is very helpful to me.
> >> As the strategies 2,coupled every thing to both rails ,you
> mentioned that we have
> >> half the total inductance and half the SSO amplitude, here is
> compared to the stripline
> >> couple to 2 vss plane or micostrip couple to 1 vss plane?
> >> Further more, for the DDR4 Pseudo-Open-Drain Logic (PODL), all
> signal should couple to vss,right?
> >>
> >> Thanks,
> >> LIU Luping
> >>
> >> -----ÓʼþÔ¼þ-----
> >> ·¢¼þÈË: steve weir [mailto:weirsi@xxxxxxxxxx]
> >> ·¢ËÍʱ¼ä: 2012Äê6ÔÂ26ÈÕ 13:45
> >> ÊÕ¼þÈË: Liuluping
> >> ³ËÍ: si-list@xxxxxxxxxxxxx
> >> Ö÷Ìâ: Re: Questions on Reference Planes for DDR3 signals
> >>
> >> There are a couple of different strategies:
> >>
> >> 1) Couple about half the lines to Vss and the remainder to Vdd. On the
> >> PCB route each line to the rail referenced end to end. This is the idea
> >> used by memories today: Data to Vss, A/C to Vdd.
> >>
> >> 2) Couple everything to both rails. Then route stripline in proportion
> >> to the coupling in the package. This theoretically can work, but is
> very
> >> restrictive on PCB routing.
> >>
> >> Lvdd and Lvss are most important at the driving end. With ODT they also
> >> matter almost as much at the Rx end. Vnoise = Lcommon*di/dt still
> >> defines common signal noise. Limit Lcommon, di/dt, or both to get
> >> acceptable Vnoise.
> >>
> >> Vtt should track the AC reference(s). If only one reference is used for
> >> a given signal line as in 1) then the decoupling is simpler.
> >>
> >> Steve
> >>
> >> On 6/25/2012 8:26 PM, Liuluping wrote:
> >>> Hi Steve:
> >>> Two places not very understand:
> >>> 1¡¢For a given di/dt * N bits
> >>> transitioning from low to high, relative to BOTH planes the di/dt is
> >>> positive. If the interconnect is completely symmetrical then we have
> >>> half the total inductance and half the SSO amplitude.
> >>> -----Is it means that the VDDIO-DQ-GND stackup can half the SSO
> noise compare to GND-DQ-GND ?
> >>> If so ,how to trade off ,as Jeff Loyer mentioned, as the noisy
> VDDQ may "eat" the margin of DQ.
> >>> 2¡¢ The signal line is going high: It is drawing positive
> >>> convention current through the die PDN and back to the PCB PDN
> through
> >>> both Lvdd and Lvss.
> >>> --- Here the Lvdd and Lvss locate at receiver side,right? And if
> the signal is ADD or CMD with VTT, is it better to decouple to both
> GND and VDDIO?
> >>>
> >>> Thanks,
> >>>
> >>> LIU Luping
> >>>
> >>> *****************************************************************
> >>> This e-mail and its attachments contain confidential information from
> >>> HUAWEI, which is intended only for the person or entity whose
> address is
> >>> listed above. Any use of the information contained herein in any way
> >>> (including, but not limited to, total or partial disclosure,
> reproduction,
> >>> or dissemination) by persons other than the intended recipient(s) is
> >>> prohibited. If you receive this e-mail in error, please notify the
> sender by
> >>> phone or e-mail immediately and delete it!
> >>> *****************************************************************
> >>>
> >>>
> >>> -----Original Message-----
> >>> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of steve weir
> >>> Sent: Saturday, June 23, 2012 7:05 AM
> >>> To: si-list@xxxxxxxxxxxxx
> >>> Subject: [SI-LIST] Re: Questions on Reference Planes for DDR3 signals
> >>>
> >>> Vinu, a completely balanced transmission path can theoretically
> divide
> >>> SSO in half. It does not cancel it. Let us suppose that we have a
> >>> completely balanced transmission path using a symmetrical
> stripline all
> >>> the way back to the die launch. For a given di/dt * N bits
> >>> transitioning from low to high, relative to BOTH planes the di/dt is
> >>> positive. If the interconnect is completely symmetrical then we have
> >>> half the total inductance and half the SSO amplitude. We do not
> cancel
> >>> the SSO. The only way to cancel SSO is to code such that the
> summation
> >>> of transitions multiplied by polarity equals zero.
> >>>
> >>> Steve.
> >>>
> >>> Msg: #6 in digest
> >>> Date: Mon, 25 Jun 2012 10:26:30 -0700
> >>> From: steve weir <weirsi@xxxxxxxxxx>
> >>> Subject: [SI-LIST] Re: Questions on Reference Planes for DDR3 signals
> >>>
> >>> On 6/25/2012 10:02 AM, Vinu Arumugham wrote:
> >>>> Steve,
> >>>>
> >>>> One can view it as two t-lines - signal/Vdd and signal/Vss - both
> with
> >>>> the same characteristic impedance and both terminated at their
> >>>> characteristic impedance - say 100 ohm.
> >>> Yes, and each of these lines couples into the driver through the
> package
> >>> inductance. The inductance of the Vss network is lumped as Lvss, and
> >>> the inductance of the Vdd network as Lvdd
> >>>> For a low-high transition, the
> >>>> pull-up structure discharges the signal/Vdd t-line and charges the
> >>>> signal/Vss t-line with ~10mA current drawn from the supply.
> >>> No, a low to high transition imposes di/dt of the same polarity into
> >>> both structures. The signal line is going high: It is drawing
> positive
> >>> convention current through the die PDN and back to the PCB PDN
> through
> >>> both Lvdd and Lvss.
> >>>
> >>>> For a
> >>>> high-low transition, the the pull-down structure discharges the
> >>>> signal/Vss t-line and the same 10mA from the supply charges the
> >>>> signal/Vdd t-line. A constant current from the supply is steered to
> >>>> charge the signal/Vss or signal/Vdd t-line. Since there is no
> switched
> >>>> current, di/dt is 0.
> >>> No, externally current the switched current is divided in two. It is
> >>> still switched. All you need to see this is to draw a black box
> around
> >>> the IC. What the signal line does is complemented by the PDN
> lines. In
> >>> order to cancel so that there is net zero current in the PDN
> >>> attachments, you have to reduce the net signal current to zero,
> such as
> >>> trivially with differential or less trivially with an Nb(N+M)q coding
> >>> scheme.
> >>>> Power noise would be limited to crowbar current or a gap in
> conduction
> >>>> between pull-up/pull-down structures. For high performance buffer
> >>>> designs, this should already be small.
> >>>>
> >>>> In the case of a Vss only referenced t-line, the power supply current
> >>>> switches between 0-20mA resulting in SSN.
> >>>>
> >>>> The bus needs to be unidirectional to take full advantage of
> >>>> symmetrically referenced signaling.
> >>>>
> >>>> Thanks,
> >>>> Vinu
> >>>>
> >
>
>
> --
> Steve Weir
> IPBLOX, LLC
> 150 N. Center St. #211
> Reno, NV 89501
> www.ipblox.com
>
> (775) 299-4236 Business
> (866) 675-4630 Toll-free
> (707) 780-1951 Fax
>
> All contents Copyright (c)2012 IPBLOX, LLC. All Rights Reserved.
> This e-mail may contain confidential material.
> If you are not the intended recipient, please destroy all records
> and notify the sender.
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> //www.freelists.org/webpage/si-list
>
> For help:
> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>
> List forum is accessible at:
> http://tech.groups.yahoo.com/group/si-list
>
> List archives are viewable at:
> //www.freelists.org/archives/si-list
>
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
--
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV 89501
www.ipblox.com
(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax
All contents Copyright (c)2012 IPBLOX, LLC. All Rights Reserved.
This e-mail may contain confidential material.
If you are not the intended recipient, please destroy all records
and notify the sender.
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
