[SI-LIST] Re: 答复: Questions on Reference Planes for DDR3 signals
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Liuluping <liuluping@xxxxxxxxxx>
- Date: Tue, 26 Jun 2012 05:09:38 -0700
There seems to be some confusion going around about the channel on the
PCB, and the package launch.
2) can only reduce the SSO in half under a special set of conditions.
That's the best it can do.
You can view 2) as taking N 50 Ohm lines and converting them to 2N
paired 100 Ohm lines, one line for each that references Vss and another
that references Vdd. If Lvdd and Lvss between the PCB and die are equal,
then the di/dt through Lvdd and Lvss are each half what it would have
been with N 50 Ohm lines referencing only Vdd or Vss with the same Lvss
or Lvdd. The assumption of equal Lvss and Lvdd is questionable. It
relies on a package designer either naively choosing the number of balls
for each rail, or planning for this balanced stripline PCB routing.
A smart package designer planning for the method 1) would allocate
enough Vdd and Vss connections to realize appropriate Lvdd and Lvss for
the number of lines that will reference each. So, if a memory controller
had 24 A/C that the designer intends should reference PCB Vdd and 128
data lines that should reference PCB Vss, then the ball pattern should
have a ratio of about 6 Vss for every Vdd. The key thing to remember is
that SSO builds across shared impedance. If the shared impedance is very
low relative to the di/dt, and there are not resonance problems, then
the SSO will be small. A very conservative package would carry one
signal return ball for each single ended signal ball.
Signals should only make absolutely necessary reference changes.
Differential or not, I recommend routing high speed data lines against a
contiguous Vss reference.
Steve
On 6/26/2012 3:19 AM, Liuluping wrote:
> Hi Steve:
> Thank you for your quickly reply, your explain is very helpful to me.
> As the strategies 2,coupled every thing to both rails ,you mentioned that we
> have
> half the total inductance and half the SSO amplitude, here is compared to the
> stripline
> couple to 2 vss plane or micostrip couple to 1 vss plane?
> Further more, for the DDR4 Pseudo-Open-Drain Logic (PODL), all signal
> should couple to vss,right?
>
> Thanks,
> LIU Luping
>
> -----邮件原件-----
> 发件人: steve weir [mailto:weirsi@xxxxxxxxxx]
> 发送时间: 2012年6月26日 13:45
> 收件人: Liuluping
> 抄送: si-list@xxxxxxxxxxxxx
> 主题: Re: Questions on Reference Planes for DDR3 signals
>
> There are a couple of different strategies:
>
> 1) Couple about half the lines to Vss and the remainder to Vdd. On the
> PCB route each line to the rail referenced end to end. This is the idea
> used by memories today: Data to Vss, A/C to Vdd.
>
> 2) Couple everything to both rails. Then route stripline in proportion
> to the coupling in the package. This theoretically can work, but is very
> restrictive on PCB routing.
>
> Lvdd and Lvss are most important at the driving end. With ODT they also
> matter almost as much at the Rx end. Vnoise = Lcommon*di/dt still
> defines common signal noise. Limit Lcommon, di/dt, or both to get
> acceptable Vnoise.
>
> Vtt should track the AC reference(s). If only one reference is used for
> a given signal line as in 1) then the decoupling is simpler.
>
> Steve
>
> On 6/25/2012 8:26 PM, Liuluping wrote:
>> Hi Steve:
>> Two places not very understand:
>> 1、For a given di/dt * N bits
>> transitioning from low to high, relative to BOTH planes the di/dt is
>> positive. If the interconnect is completely symmetrical then we have
>> half the total inductance and half the SSO amplitude.
>> -----Is it means that the VDDIO-DQ-GND stackup can half the SSO noise
>> compare to GND-DQ-GND ?
>> If so ,how to trade off ,as Jeff Loyer mentioned, as the noisy VDDQ may
>> "eat" the margin of DQ.
>> 2、 The signal line is going high: It is drawing positive
>> convention current through the die PDN and back to the PCB PDN through
>> both Lvdd and Lvss.
>> --- Here the Lvdd and Lvss locate at receiver side,right? And if the signal
>> is ADD or CMD with VTT, is it better to decouple to both GND and VDDIO?
>>
>> Thanks,
>>
>> LIU Luping
>>
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>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
>> Behalf Of steve weir
>> Sent: Saturday, June 23, 2012 7:05 AM
>> To: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: Questions on Reference Planes for DDR3 signals
>>
>> Vinu, a completely balanced transmission path can theoretically divide
>> SSO in half. It does not cancel it. Let us suppose that we have a
>> completely balanced transmission path using a symmetrical stripline all
>> the way back to the die launch. For a given di/dt * N bits
>> transitioning from low to high, relative to BOTH planes the di/dt is
>> positive. If the interconnect is completely symmetrical then we have
>> half the total inductance and half the SSO amplitude. We do not cancel
>> the SSO. The only way to cancel SSO is to code such that the summation
>> of transitions multiplied by polarity equals zero.
>>
>> Steve.
>>
>> Msg: #6 in digest
>> Date: Mon, 25 Jun 2012 10:26:30 -0700
>> From: steve weir <weirsi@xxxxxxxxxx>
>> Subject: [SI-LIST] Re: Questions on Reference Planes for DDR3 signals
>>
>> On 6/25/2012 10:02 AM, Vinu Arumugham wrote:
>>> Steve,
>>>
>>> One can view it as two t-lines - signal/Vdd and signal/Vss - both with
>>> the same characteristic impedance and both terminated at their
>>> characteristic impedance - say 100 ohm.
>> Yes, and each of these lines couples into the driver through the package
>> inductance. The inductance of the Vss network is lumped as Lvss, and
>> the inductance of the Vdd network as Lvdd
>>> For a low-high transition, the
>>> pull-up structure discharges the signal/Vdd t-line and charges the
>>> signal/Vss t-line with ~10mA current drawn from the supply.
>> No, a low to high transition imposes di/dt of the same polarity into
>> both structures. The signal line is going high: It is drawing positive
>> convention current through the die PDN and back to the PCB PDN through
>> both Lvdd and Lvss.
>>
>>> For a
>>> high-low transition, the the pull-down structure discharges the
>>> signal/Vss t-line and the same 10mA from the supply charges the
>>> signal/Vdd t-line. A constant current from the supply is steered to
>>> charge the signal/Vss or signal/Vdd t-line. Since there is no switched
>>> current, di/dt is 0.
>> No, externally current the switched current is divided in two. It is
>> still switched. All you need to see this is to draw a black box around
>> the IC. What the signal line does is complemented by the PDN lines. In
>> order to cancel so that there is net zero current in the PDN
>> attachments, you have to reduce the net signal current to zero, such as
>> trivially with differential or less trivially with an Nb(N+M)q coding
>> scheme.
>>> Power noise would be limited to crowbar current or a gap in conduction
>>> between pull-up/pull-down structures. For high performance buffer
>>> designs, this should already be small.
>>>
>>> In the case of a Vss only referenced t-line, the power supply current
>>> switches between 0-20mA resulting in SSN.
>>>
>>> The bus needs to be unidirectional to take full advantage of
>>> symmetrically referenced signaling.
>>>
>>> Thanks,
>>> Vinu
>>>
>
--
Steve Weir
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