[SI-LIST] Re: Questions on Reference Planes for DDR3 signals
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 27 Jun 2012 12:00:16 -0700
Vinu, no that is not correct. You need to lose the electron hose model
and use moving wavefronts. All one needs to excite a cavity, even a
closed one like a beer can is: A cavity with conductive walls,
dielectric volume, and a launch mechanism. A signal conductor in the
dielectric provides the launch mechanism on digital PCBs. If we obtain
a beer can and pierce it with an ice pick ( being careful to preserve
the important contents for later "disposal" ), and then insert a small
insulating grommet into each hole and then thread a wire through, we can
then connect one port of a VNA to one end of the wire and the can, and
another port to the other, and then entertain ourselves observing the
S11 and S21 plots while properly disposing of the saved can contents.
The plots will show the resonant frequency of the beer can. They can
only do that because we successfully excite the cavity.
Best Regards,
Steve.
On 6/27/2012 9:58 AM, Vinu Arumugham wrote:
> Steve,
>
> To excite the cavity there must be a current in Vddq with an image
> current on Vss in the opposite direction. In SRS, the image current for
> the signal is of equal magnitude and direction on both planes. So the
> cavity cannot be excited. As for via transitions exciting the cavity, an
> SRS signal via would need a Vddq via and Vss via (but no bypass
> capacitors) to minimize excitation.
>
> Thanks,
> Vinu
>
> On 06/26/2012 08:02 PM, steve weir wrote:
>> Vinu, using two return planes does not cancel the current, it just
>> divides it. The cavity is not only excited, but because it must
>> maintain DC isolation, we have a much harder time stitching it, making
>> it harder to avoid resonance problems than a cavity that is Vss only.
>>
>> Best Regards,
>>
>>
>> Steve.
>> On 6/26/2012 11:10 AM, Vinu Arumugham wrote:
>>> I have included a drawing which will hopefully clear things up. I have
>>> added an inductor in series with the supply to emphasize that the supply
>>> can be AC high impedance. All currents in green according to my analysis
>>> are DC. Blue represents logic low currents and red logic high.
>>>
>>> https://docs.google.com/open?id=0B1SXvUJqinZYSHBiNWRNeGZGYjQ
>>>
>>> In differential signaling, a constant current drawn from the supply is
>>> steered into the true or complement lines. In symmetrically referenced
>>> signaling (SRS), the signal/Vdd line can be viewed as the true and the
>>> signal/Vss line can be viewed as the complement. In SRS, as in
>>> differential signaling, a constant current from the supply is steered
>>> into one or the other line.
>>>
>>> There is no current injected into Vdd that needs to return on Vss. This
>>> means the Vdd/Vss cavity is not excited.
>>>
>>> Thanks,
>>> Vinu
>>>
>>> On 06/25/2012 10:26 AM, steve weir wrote:
>>>> On 6/25/2012 10:02 AM, Vinu Arumugham wrote:
>>>>> Steve,
>>>>>
>>>>> One can view it as two t-lines - signal/Vdd and signal/Vss - both with
>>>>> the same characteristic impedance and both terminated at their
>>>>> characteristic impedance - say 100 ohm.
>>>> Yes, and each of these lines couples into the driver through the package
>>>> inductance. The inductance of the Vss network is lumped as Lvss, and
>>>> the inductance of the Vdd network as Lvdd
>>>>> For a low-high transition, the
>>>>> pull-up structure discharges the signal/Vdd t-line and charges the
>>>>> signal/Vss t-line with ~10mA current drawn from the supply.
>>>> No, a low to high transition imposes di/dt of the same polarity into
>>>> both structures. The signal line is going high: It is drawing positive
>>>> convention current through the die PDN and back to the PCB PDN through
>>>> both Lvdd and Lvss.
>>>>
>>>>> For a
>>>>> high-low transition, the the pull-down structure discharges the
>>>>> signal/Vss t-line and the same 10mA from the supply charges the
>>>>> signal/Vdd t-line. A constant current from the supply is steered to
>>>>> charge the signal/Vss or signal/Vdd t-line. Since there is no switched
>>>>> current, di/dt is 0.
>>>> No, externally current the switched current is divided in two. It is
>>>> still switched. All you need to see this is to draw a black box around
>>>> the IC. What the signal line does is complemented by the PDN lines. In
>>>> order to cancel so that there is net zero current in the PDN
>>>> attachments, you have to reduce the net signal current to zero, such as
>>>> trivially with differential or less trivially with an Nb(N+M)q coding
>>>> scheme.
>>>>> Power noise would be limited to crowbar current or a gap in conduction
>>>>> between pull-up/pull-down structures. For high performance buffer
>>>>> designs, this should already be small.
>>>>>
>>>>> In the case of a Vss only referenced t-line, the power supply current
>>>>> switches between 0-20mA resulting in SSN.
>>>>>
>>>>> The bus needs to be unidirectional to take full advantage of
>>>>> symmetrically referenced signaling.
>>>>>
>>>>> Thanks,
>>>>> Vinu
>>>>>
>>>>>
>>>>> On 06/22/2012 10:05 PM, steve weir wrote:
>>>>>> Vinu, a completely balanced transmission path can theoretically divide
>>>>>> SSO in half. It does not cancel it. Let us suppose that we have a
>>>>>> completely balanced transmission path using a symmetrical stripline all
>>>>>> the way back to the die launch. For a given di/dt * N bits
>>>>>> transitioning from low to high, relative to BOTH planes the di/dt is
>>>>>> positive. If the interconnect is completely symmetrical then we have
>>>>>> half the total inductance and half the SSO amplitude. We do not cancel
>>>>>> the SSO. The only way to cancel SSO is to code such that the summation
>>>>>> of transitions multiplied by polarity equals zero.
>>>>>>
>>>>>> Steve.
>>>>>>
>>>>>> On 6/22/2012 10:08 AM, Vinu Arumugham wrote:
>>>>>>> Steve,
>>>>>>>
>>>>>>> A network DRAM package we looked at had signal lines referenced to both
>>>>>>> Vddq and Vss. It also had a pinout where the data pins were interspersed
>>>>>>> with Vddq and Vss.
>>>>>>>
>>>>>>> If the DDR3 DRAM package routing is symmetrically referenced to
>>>>>>> Vddq/Vss, it enables construction of a signal path that is symmetrically
>>>>>>> referenced end-to-end (non-DIMM applications). Along with the fact that
>>>>>>> data lines are thevenin terminated to Vddq/Vss, it creates a special
>>>>>>> signaling configuration where theoretically SSO would be zero.
>>>>>>>
>>>>>>> Thanks,
>>>>>>> Vinu
>>>>>>>
>>>>>>> On 06/21/2012 09:23 PM, steve weir wrote:
>>>>>>>> Vinu this was the practice with the last packages I looked at several
>>>>>>>> years ago.
>>>>>>>>
>>>>>>>> Steve
>>>>>>>> On 6/21/2012 9:49 AM, Vinu Arumugham wrote:
>>>>>>>>> Steve,
>>>>>>>>>
>>>>>>>>> Have you verified that memory packages reference data lines only to
>>>>>>>>> Vss?
>>>>>>>>> The memory pinout suggests that data lines are referenced to both Vss
>>>>>>>>> and Vddq.
>>>>>>>>>
>>>>>>>>> Thanks,
>>>>>>>>> Vinu
>>>>>>>>>
>>>>>>>>> On 06/21/2012 01:39 AM, steve weir wrote:
>>>>>>>>>> Hirshtal, this all amounts to reducing signal disturbance.
>>>>>>>>>> Unfortunately, this is another case of: "It all depends." The data
>>>>>>>>>> signals constitute the higher data rates as well as the greater
>>>>>>>>>> number
>>>>>>>>>> SSOs, so they deserve more care than the A/C signals. However, if
>>>>>>>>>> you
>>>>>>>>>> want reliable operation at speed, reasonable care must be employed
>>>>>>>>>> with
>>>>>>>>>> both. You have a few basic options:
>>>>>>>>>>
>>>>>>>>>> 1. Follow a proven topology exactly as though your life depends on
>>>>>>>>>> it.
>>>>>>>>>> Pray that the gods of reference designs will reward your dedicated
>>>>>>>>>> obedience by blessing your effort.
>>>>>>>>>>
>>>>>>>>>> 2. Develop and evaluate design rules that are suitable to your
>>>>>>>>>> particular situation. Tool sets are available to evaluate different
>>>>>>>>>> topologies, such as from Si-Soft. If you don't have the tools, the
>>>>>>>>>> budget, or the time, then you can lean on an outside service to do
>>>>>>>>>> this
>>>>>>>>>> for you.
>>>>>>>>>>
>>>>>>>>>> 3. Try to develop rules ad-hoc without checking and hope that Murphy
>>>>>>>>>> does not decide to amuse himself at your expense. The more
>>>>>>>>>> conservative
>>>>>>>>>> the rules you set, the more likely you can save yourself the wrath of
>>>>>>>>>> Murphy.
>>>>>>>>>>
>>>>>>>>>> Slides 14 and 15 of this presentation available on my web-site
>>>>>>>>>> illustrate what you face with different routing topologies:
>>>>>>>>>> http://www.ipblox.com/pubs/SVCEMC_May_2005/capacitor_placement_public_b.pdf
>>>>>>>>>>
>>>>>>>>>> A couple of comments: Memory packages and DIMMs reference data
>>>>>>>>>> lines to
>>>>>>>>>> Vss. DIMMs reference A/C to VDDQ. This was done to support low
>>>>>>>>>> layer
>>>>>>>>>> count PCBs. It works. You will avoid introducing extra noise and
>>>>>>>>>> cross-talk by extending those references in your channel end to end.
>>>>>>>>>> What your memory controllers reference varies. Any reference change
>>>>>>>>>> you
>>>>>>>>>> introduce will inject energy between the the references used. This
>>>>>>>>>> can
>>>>>>>>>> be handled, but requires work and more analysis. And unless the
>>>>>>>>>> design
>>>>>>>>>> is low performance, it usually imposes more cost for equal
>>>>>>>>>> performance.
>>>>>>>>>>
>>>>>>>>>> A final note: Always treat clock with the utmost care. Barring some
>>>>>>>>>> terrible cost impact a continuous Vss reference is a good way to
>>>>>>>>>> treat
>>>>>>>>>> clocks.
>>>>>>>>>>
>>>>>>>>>> Steve
>>>>>>>>>> On 6/21/2012 1:42 AM, Hirshtal Itzhak wrote:
>>>>>>>>>>> Hello all,
>>>>>>>>>>> I've been looking at DDR3 layout guides from Micron and from some
>>>>>>>>>>> manufacturers of DDR3 controller devices and haven't found a clear
>>>>>>>>>>> recommendation for how to deal with the issue of reference planes
>>>>>>>>>>> for DDR3 interfaces in a stripline configuration. Also, there are
>>>>>>>>>>> some other "reference-plane" issues which I hope someone can
>>>>>>>>>>> clarify.
>>>>>>>>>>>
>>>>>>>>>>> So here are the questions I haven't found a clear answer for:
>>>>>>>>>>>
>>>>>>>>>>> (1) Almost all recommendations that I've
>>>>>>>>>>> found are to route data-group signals "adjacent to a solid GND
>>>>>>>>>>> Layer". Can I, therefore, route them adjacent to both a GND and a
>>>>>>>>>>> Power plane in a stripline configuration? Does it matter if the
>>>>>>>>>>> stripline is symmetric (relative to the 2 ref planes) or not?
>>>>>>>>>>> (2) Almost all recommendations that I've
>>>>>>>>>>> found are to route address/command/control signals "adjacent to a
>>>>>>>>>>> solid Power or GND Layer". Can I route them adjacent to a Power
>>>>>>>>>>> plane with a voltage different than the DDR3-1.5Volt VDD?
>>>>>>>>>>> (3) If DDR-VDD is required, can I use
>>>>>>>>>>> another solid Power plane as the other plane in stripline
>>>>>>>>>>> configurations (provided the 1st plane is VDD)?
>>>>>>>>>>> (4) What reference plane is recommended
>>>>>>>>>>> for the Clock pair? Micron, for example, doesn't say anything on
>>>>>>>>>>> this matter, but some other manufacturers recommend using only a
>>>>>>>>>>> GND plane. Is this true, as far as you know?
>>>>>>>>>>>
>>>>>>>>>>> Thanks in advance for your help!
>>>>>>>>>>>
>>>>>>>>>>> Itzhak Hirshtal
>>>>>>>>>>> Elta Systems
>>>>>>>>>>>
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