[SI-LIST] Re: Questions on Reference Planes for DDR3 signals
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: vinu@xxxxxxxxx
- Date: Wed, 27 Jun 2012 16:16:30 -0400
Vinu,
sorry, wrong answer.
So, one vss via dangling in the cavity
One vdd via dangling in the cavity
how is the AC short necessary to suppress cavity waves made?
you have wrong ideas regarding what a via can do when only connected to
one net.
Scott
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On 6/27/2012 4:03 PM, Vinu Arumugham wrote:
> Scott,
>
> For a signal going from one Vddq/Vss cavity to another, you only need a
> Vddq via and a Vss via. A capacitor is not needed.
>
> Thanks,
> Vinu
>
> On 06/27/2012 12:36 PM, Scott McMorrow wrote:
>> That would be quite correct, Vinu. You now understand. In a Vss/Vcc
>> referenced stripline, there is no effective way to stitch the planes.
>> In a Vss/Vss reference stripline there is. In one we can stitch with
>> vias. In the other, we gotta go through caps. For a DDR signal
>> switching in the vicinity of 1 GHz, the ain't no bypass cap that can
>> effectively help with Vss/Vcc referencing. Cavity injection occurs, is
>> not suppressed, and tends to rattle around, resonate, and cause worst
>> SSO than just inductive bounce. Steve and I showed this in our
>> DesignCon paper from several years ago.
>>
>>
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