Unless the signal paths are very long, loss in the traces will not be an
issue with modern serdes. Some from Xilinx can tolerate 38 db loss at 28
Gb/S!
As an aside, differential impedance is not what counts. Two good 50 ohm
lines is what diff signaling requires.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Carson Au
Sent: Thursday, November 3, 2016 5:07 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] HDI and SERDES Channels
Hi Experts,
From my understanding, HDI build-up layers require thin prepreg layers,
leading to very thin trace widths for 100ohm differential impedance control
- and your high speed serial links would suffer great conductor loss.
How do you mitigate against this?
If your design has many build-up layers with thin build-up layers on either
side of your stripline, then it is impossible to even get something like
100um (4mil) trace widths for your 100 ohm differential pairs!!
Regards,
Carson
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