Mostly it is people working too hard on the layout! The caveat being that when
rates get above about 5 Gb/S how one uses vias can severely degrade
performance. Several papers have been presented at DesignCon on that topic.
From: Carson Au [mailto:carson.au@xxxxxxxxx] ;
Sent: Thursday, November 3, 2016 1:01 PM
To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
Cc: dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: HDI and SERDES Channels
If loss isn't usually the problem, does that mean usually smooth copper usually
doesn't have to be considered in the design (or are there more benefits to
smooth copper than just lower loss?)
Lee, what are the top problems in modern SERDES layout in your opinion (besides
the fibre weave effect)?
On Fri, Nov 4, 2016 at 3:21 AM, Lee Ritchey <leeritchey@xxxxxxxxxxxxx
<mailto:leeritchey@xxxxxxxxxxxxx> > wrote:
Before I would do any of that, I would do some analysis to see what the
losses would be if normal striplines are used. My experience is that this
extra work would not be necessary.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx>
[mailto:si-list-bounce@xxxxxxxxxxxxx ;<mailto:si-list-bounce@xxxxxxxxxxxxx> ] On
Behalf Of Loyer, Jeff (Redacted sender "jwloyer" for DMARC)
Sent: Thursday, November 3, 2016 8:16 AM
To: carson.au@xxxxxxxxx <mailto:carson.au@xxxxxxxxx> ; si-list@xxxxxxxxxxxxx
<mailto:si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: HDI and SERDES Channels
I think you'd have to void the layers above or below your signal traces.
For instance, I can imagine routing the longest lengths on the outermost
layers of the "core" of a build-up stackup and voiding layers above those
traces to allow me to widen the traces (they would also be relatively thick,
further lowering loss). You'd want a solid plane above them somewhere, but
it doesn't have to be the adjacent layer. You'd also have to be careful to
specify smooth copper on those layers, else the manufacturer will probably
undo your great efforts by putting rough copper on them.
Jeff
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx>
[mailto:si-list-bounce@xxxxxxxxxxxxx ;<mailto:si-list-bounce@xxxxxxxxxxxxx> ] On
Behalf Of Carson Au
Sent: Thursday, November 03, 2016 5:07 AM
To: si-list@xxxxxxxxxxxxx <mailto:si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] HDI and SERDES Channels
Hi Experts,
From my understanding, HDI build-up layers require thin prepreg layers,
leading to very thin trace widths for 100ohm differential impedance control
- and your high speed serial links would suffer great conductor loss.
How do you mitigate against this?
If your design has many build-up layers with thin build-up layers on either
side of your stripline, then it is impossible to even get something like
100um (4mil) trace widths for your 100 ohm differential pairs!!
Regards,
Carson
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