Carson,
You can go around and around and worry about issues that are not important but
miss issues that throttle your performance. You donât need smooth copper
for 5Gbpsec for moderate to long traces since the Nyquist frequency is only
2.5GHz.
Build a custom platform test vehicle using your stackup and copper that
includes structures for material identification, loss model validation, via
structures, SE and DIFF nets, along with a host of other structures providing
validation of your 3D EM to measurement tool. Send me a pm if you want help.
- Al
Products for the Signal Integrity Practitioner
Alfred P. Neves
Chief Technologist
Office: 503-679-2429
www.wildrivertech.com <http://www.wildrivertech.com/>
2015 Best In Design&Test Finalist
On Nov 3, 2016, at 1:19 PM, Carson Au <carson.au@xxxxxxxxx> wrote:
For example, let's just say some pedestrian 10Gb/s channels.
Are layer-transition via anti-pads important at those speeds? Can I
generally eliminate anti-pads for these channels to gain better routing
density?
If via stubs manifest themselves as losses on the channel, can I not care
about these stubs because now the SERDES receiver can recover from extreme
losses in the channel?
On Fri, Nov 4, 2016 at 7:10 AM, John <johndp@xxxxxxxx
<mailto:johndp@xxxxxxxx>> wrote:
What is and what isn't important in your design is largely dependant on
the speed you want to go. So giving the list an indication of the operating
bit rate of your Serdes will enable us to better answer your question
Regards
John
Sent from my Sony Xperia⢠smartphone
---- Carson Au wrote ----
If loss isn't usually the problem, does that mean usually smooth copper
usually doesn't have to be considered in the design (or are there more
benefits to smooth copper than just lower loss?)
Lee, what are the top problems in modern SERDES layout in your opinion
(besides the fibre weave effect)?
On Fri, Nov 4, 2016 at 3:21 AM, Lee Ritchey <leeritchey@xxxxxxxxxxxxx
<mailto:leeritchey@xxxxxxxxxxxxx>>
wrote:
Before I would do any of that, I would do some analysis to see what thethis
losses would be if normal striplines are used. My experience is that
extra work would not be necessary.but
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx>
[mailto:si-list-bounce@xxxxxxxxxxxxx ;<mailto:si-list-bounce@xxxxxxxxxxxxx>]
On
Behalf Of Loyer, Jeff (Redacted sender "jwloyer" for DMARC)
Sent: Thursday, November 3, 2016 8:16 AM
To: carson.au@xxxxxxxxx <mailto:carson.au@xxxxxxxxx>; si-list@xxxxxxxxxxxxx
<mailto:si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: HDI and SERDES Channels
I think you'd have to void the layers above or below your signal traces.
For instance, I can imagine routing the longest lengths on the outermost
layers of the "core" of a build-up stackup and voiding layers above those
traces to allow me to widen the traces (they would also be relatively
thick,
further lowering loss). You'd want a solid plane above them somewhere,
it doesn't have to be the adjacent layer. You'd also have to be carefulto
specify smooth copper on those layers, else the manufacturer willprobably
undo your great efforts by putting rough copper on them.control
Jeff
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx>
[mailto:si-list-bounce@xxxxxxxxxxxxx ;<mailto:si-list-bounce@xxxxxxxxxxxxx>]
On
Behalf Of Carson Au
Sent: Thursday, November 03, 2016 5:07 AM
To: si-list@xxxxxxxxxxxxx <mailto:si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] HDI and SERDES Channels
Hi Experts,
From my understanding, HDI build-up layers require thin prepreg layers,
leading to very thin trace widths for 100ohm differential impedance
- and your high speed serial links would suffer great conductor loss.either
How do you mitigate against this?
If your design has many build-up layers with thin build-up layers on
side of your stripline, then it is impossible to even get something like
100um (4mil) trace widths for your 100 ohm differential pairs!!
Regards,
Carson
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